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Wed, 11 Mar 2026 12:39:27 -0700 (PDT) Date: Wed, 11 Mar 2026 22:39:24 +0300 From: Dan Carpenter To: Linus Walleij , AKASHI Takahiro Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , arm-scmi@vger.kernel.org Subject: [PATCH v3 7/7] gpio: add pinctrl based generic gpio driver Message-ID: <93920f541564bc4e6aaf0f2b6df2f5aca721d452.1773150895.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: AKASHI Takahiro The ARM SCMI pinctrl protocol allows GPIO access. Instead of creating a new SCMI gpio driver, this driver is a generic GPIO driver that uses standard pinctrl interfaces. Signed-off-by: AKASHI Takahiro Signed-off-by: Dan Carpenter Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-by-pinctrl.c | 124 +++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 drivers/gpio/gpio-by-pinctrl.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b45fb799e36c..4c8d2589c412 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -246,6 +246,13 @@ config GPIO_BRCMSTB help Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs. =20 +config GPIO_BY_PINCTRL + tristate "GPIO support based on a pure pin control backend" + depends on GPIOLIB + help + Select this option to support GPIO devices based solely on pin + control. This is used to do GPIO over the ARM SCMI protocol. + config GPIO_CADENCE tristate "Cadence GPIO support" depends on OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c05f7d795c43..20d4a57afdaa 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_GPIO_BD9571MWV) +=3D gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BLZP1600) +=3D gpio-blzp1600.o obj-$(CONFIG_GPIO_BRCMSTB) +=3D gpio-brcmstb.o obj-$(CONFIG_GPIO_BT8XX) +=3D gpio-bt8xx.o +obj-$(CONFIG_GPIO_BY_PINCTRL) +=3D gpio-by-pinctrl.o obj-$(CONFIG_GPIO_CADENCE) +=3D gpio-cadence.o obj-$(CONFIG_GPIO_CGBC) +=3D gpio-cgbc.o obj-$(CONFIG_GPIO_CLPS711X) +=3D gpio-clps711x.o diff --git a/drivers/gpio/gpio-by-pinctrl.c b/drivers/gpio/gpio-by-pinctrl.c new file mode 100644 index 000000000000..c1fed14c9d01 --- /dev/null +++ b/drivers/gpio/gpio-by-pinctrl.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2023 Linaro Inc. +// Author: AKASHI takahiro + +#include +#include +#include +#include +#include +#include +#include "gpiolib.h" + +struct pin_control_gpio_priv { + struct gpio_chip chip; +}; + +static int pin_control_gpio_get_direction(struct gpio_chip *gc, unsigned i= nt offset) +{ + unsigned long config; + bool in, out; + int ret; + + config =3D PIN_CONFIG_INPUT_ENABLE; + ret =3D pinctrl_gpio_get_config(gc, offset, &config); + if (ret) + return ret; + in =3D config; + + config =3D PIN_CONFIG_OUTPUT_ENABLE; + ret =3D pinctrl_gpio_get_config(gc, offset, &config); + if (ret) + return ret; + out =3D config; + + /* Consistency check - in theory both can be enabled! */ + if (in && !out) + return GPIO_LINE_DIRECTION_IN; + if (!in && out) + return GPIO_LINE_DIRECTION_OUT; + + return -EINVAL; +} + +static int pin_control_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + return pinctrl_gpio_direction_output(chip, offset); +} + +static int pin_control_gpio_get(struct gpio_chip *chip, unsigned int offse= t) +{ + unsigned long config; + int ret; + + config =3D PIN_CONFIG_LEVEL; + ret =3D pinctrl_gpio_get_config(chip, offset, &config); + if (ret) + return ret; + + return !!config; +} + +static int pin_control_gpio_set(struct gpio_chip *chip, unsigned int offse= t, + int val) +{ + unsigned long config; + + config =3D PIN_CONF_PACKED(PIN_CONFIG_LEVEL, val); + return pinctrl_gpio_set_config(chip, offset, config); +} + +static int pin_control_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pin_control_gpio_priv *priv; + struct gpio_chip *chip; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + chip =3D &priv->chip; + chip->label =3D dev_name(dev); + chip->parent =3D dev; + chip->base =3D -1; + + chip->request =3D gpiochip_generic_request; + chip->free =3D gpiochip_generic_free; + chip->get_direction =3D pin_control_gpio_get_direction; + chip->direction_input =3D pinctrl_gpio_direction_input; + chip->direction_output =3D pin_control_gpio_direction_output; + chip->get =3D pin_control_gpio_get; + chip->set =3D pin_control_gpio_set; + chip->set_config =3D gpiochip_generic_config; + + ret =3D devm_gpiochip_add_data(dev, chip, priv); + if (ret) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id pin_control_gpio_match[] =3D { + { .compatible =3D "scmi-pinctrl-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pin_control_gpio_match); + +static struct platform_driver pin_control_gpio_driver =3D { + .probe =3D pin_control_gpio_probe, + .driver =3D { + .name =3D "pin-control-gpio", + .of_match_table =3D pin_control_gpio_match, + }, +}; +module_platform_driver(pin_control_gpio_driver); + +MODULE_AUTHOR("AKASHI Takahiro "); +MODULE_DESCRIPTION("Pinctrl based GPIO driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0