From nobody Wed Sep 10 05:33:15 2025 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05DC330DEC5; Tue, 9 Sep 2025 07:34:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757403247; cv=none; b=k9Rp3DAfnd18rqsiWiJ7bevKldbdxskPi13Dg0QM/nFVIZhJsVPdDoheletqYWsTb2wfbvDIqIRZNVYsFWkLDXPXs7cx2PMP0PHVy3QMi7ttdd0WLSKGCfLz95cPlgjrEzXKoy+f/wiojY5G397NGDYfqU77x/8j7gEFip/rK2c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757403247; c=relaxed/simple; bh=5FMNIiSZBBTXpXTec8AIZmd4GbkghmicIv5a7pA8+tk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Twiu9jkHwSQQWY77kTRD9ZS8VOmAIaneli9lVX/8v6xdR23bTNVCn9DrmmickT63USr9j76YPmILXRQk3YnWJkX3bmdDBusP/UF2CT8TwYqUb51J9BKmAKczBnQZSLVjtISnqYtRKE9jVnZZKXXivK9Wl7ONbnysRmC8DslPWWo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4cLb8h1PGsz1R9Jh; Tue, 9 Sep 2025 15:31:00 +0800 (CST) Received: from kwepemf100013.china.huawei.com (unknown [7.202.181.12]) by mail.maildlp.com (Postfix) with ESMTPS id 3C58B14013B; Tue, 9 Sep 2025 15:34:02 +0800 (CST) Received: from DESKTOP-62GVMTR.china.huawei.com (10.174.189.55) by kwepemf100013.china.huawei.com (7.202.181.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 9 Sep 2025 15:34:00 +0800 From: Fan Gong To: Fan Gong , Zhu Yikai CC: , , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Andrew Lunn , , Jonathan Corbet , Bjorn Helgaas , luosifu , Xin Guo , Shen Chenyang , Zhou Shuai , Wu Like , Shi Jing , Luo Yang , Meny Yossefi , Gur Stavi , Lee Trager , Michael Ellerman , Vadim Fedorenko , Suman Ghosh , Przemek Kitszel , Joe Damato , Christophe JAILLET Subject: [PATCH net-next v05 07/14] hinic3: Queue pair endianness improvements Date: Tue, 9 Sep 2025 15:33:32 +0800 Message-ID: <90167074ae79a7e90a0fea0e38c32bbe8203231e.1757401320.git.zhuyikai1@h-partners.com> X-Mailer: git-send-email 2.51.0.windows.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemf100013.china.huawei.com (7.202.181.12) Content-Type: text/plain; charset="utf-8" Explicitly use little-endian & big-endian structs to support big endian hosts. Co-developed-by: Zhu Yikai Signed-off-by: Zhu Yikai Signed-off-by: Fan Gong Reviewed-by: Vadim Fedorenko --- .../ethernet/huawei/hinic3/hinic3_nic_io.h | 15 ++-- .../net/ethernet/huawei/hinic3/hinic3_rx.c | 10 +-- .../net/ethernet/huawei/hinic3/hinic3_rx.h | 24 +++--- .../net/ethernet/huawei/hinic3/hinic3_tx.c | 81 ++++++++++--------- .../net/ethernet/huawei/hinic3/hinic3_tx.h | 18 ++--- 5 files changed, 79 insertions(+), 69 deletions(-) diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h b/drivers/n= et/ethernet/huawei/hinic3/hinic3_nic_io.h index 865ba6878c48..1808d37e7cf7 100644 --- a/drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h +++ b/drivers/net/ethernet/huawei/hinic3/hinic3_nic_io.h @@ -75,8 +75,8 @@ static inline u16 hinic3_get_sq_hw_ci(const struct hinic3= _io_queue *sq) #define DB_CFLAG_DP_RQ 1 =20 struct hinic3_nic_db { - u32 db_info; - u32 pi_hi; + __le32 db_info; + __le32 pi_hi; }; =20 static inline void hinic3_write_db(struct hinic3_io_queue *queue, int cos, @@ -84,11 +84,12 @@ static inline void hinic3_write_db(struct hinic3_io_que= ue *queue, int cos, { struct hinic3_nic_db db; =20 - db.db_info =3D DB_INFO_SET(DB_SRC_TYPE, TYPE) | - DB_INFO_SET(cflag, CFLAG) | - DB_INFO_SET(cos, COS) | - DB_INFO_SET(queue->q_id, QID); - db.pi_hi =3D DB_PI_HIGH(pi); + db.db_info =3D + cpu_to_le32(DB_INFO_SET(DB_SRC_TYPE, TYPE) | + DB_INFO_SET(cflag, CFLAG) | + DB_INFO_SET(cos, COS) | + DB_INFO_SET(queue->q_id, QID)); + db.pi_hi =3D cpu_to_le32(DB_PI_HIGH(pi)); =20 writeq(*((u64 *)&db), DB_ADDR(queue, pi)); } diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_rx.c b/drivers/net/e= thernet/huawei/hinic3/hinic3_rx.c index 860163e9d66c..ac04e3a192ad 100644 --- a/drivers/net/ethernet/huawei/hinic3/hinic3_rx.c +++ b/drivers/net/ethernet/huawei/hinic3/hinic3_rx.c @@ -66,8 +66,8 @@ static void rq_wqe_buf_set(struct hinic3_io_queue *rq, ui= nt32_t wqe_idx, struct hinic3_rq_wqe *rq_wqe; =20 rq_wqe =3D get_q_element(&rq->wq.qpages, wqe_idx, NULL); - rq_wqe->buf_hi_addr =3D upper_32_bits(dma_addr); - rq_wqe->buf_lo_addr =3D lower_32_bits(dma_addr); + rq_wqe->buf_hi_addr =3D cpu_to_le32(upper_32_bits(dma_addr)); + rq_wqe->buf_lo_addr =3D cpu_to_le32(lower_32_bits(dma_addr)); } =20 static u32 hinic3_rx_fill_buffers(struct hinic3_rxq *rxq) @@ -279,7 +279,7 @@ static int recv_one_pkt(struct hinic3_rxq *rxq, struct = hinic3_rq_cqe *rx_cqe, if (skb_is_nonlinear(skb)) hinic3_pull_tail(skb); =20 - offload_type =3D rx_cqe->offload_type; + offload_type =3D le32_to_cpu(rx_cqe->offload_type); hinic3_rx_csum(rxq, offload_type, status, skb); =20 num_lro =3D RQ_CQE_STATUS_GET(status, NUM_LRO); @@ -311,14 +311,14 @@ int hinic3_rx_poll(struct hinic3_rxq *rxq, int budget) while (likely(nr_pkts < budget)) { sw_ci =3D rxq->cons_idx & rxq->q_mask; rx_cqe =3D rxq->cqe_arr + sw_ci; - status =3D rx_cqe->status; + status =3D le32_to_cpu(rx_cqe->status); if (!RQ_CQE_STATUS_GET(status, RXDONE)) break; =20 /* make sure we read rx_done before packet length */ rmb(); =20 - vlan_len =3D rx_cqe->vlan_len; + vlan_len =3D le32_to_cpu(rx_cqe->vlan_len); pkt_len =3D RQ_CQE_SGE_GET(vlan_len, LEN); if (recv_one_pkt(rxq, rx_cqe, pkt_len, vlan_len, status)) break; diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_rx.h b/drivers/net/e= thernet/huawei/hinic3/hinic3_rx.h index 1cca21858d40..e7b496d13a69 100644 --- a/drivers/net/ethernet/huawei/hinic3/hinic3_rx.h +++ b/drivers/net/ethernet/huawei/hinic3/hinic3_rx.h @@ -27,21 +27,21 @@ =20 /* RX Completion information that is provided by HW for a specific RX WQE = */ struct hinic3_rq_cqe { - u32 status; - u32 vlan_len; - u32 offload_type; - u32 rsvd3; - u32 rsvd4; - u32 rsvd5; - u32 rsvd6; - u32 pkt_info; + __le32 status; + __le32 vlan_len; + __le32 offload_type; + __le32 rsvd3; + __le32 rsvd4; + __le32 rsvd5; + __le32 rsvd6; + __le32 pkt_info; }; =20 struct hinic3_rq_wqe { - u32 buf_hi_addr; - u32 buf_lo_addr; - u32 cqe_hi_addr; - u32 cqe_lo_addr; + __le32 buf_hi_addr; + __le32 buf_lo_addr; + __le32 cqe_hi_addr; + __le32 cqe_lo_addr; }; =20 struct hinic3_rx_info { diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_tx.c b/drivers/net/e= thernet/huawei/hinic3/hinic3_tx.c index f1c745ee3087..8671bc2e1316 100644 --- a/drivers/net/ethernet/huawei/hinic3/hinic3_tx.c +++ b/drivers/net/ethernet/huawei/hinic3/hinic3_tx.c @@ -81,10 +81,10 @@ static int hinic3_tx_map_skb(struct net_device *netdev,= struct sk_buff *skb, =20 dma_info[0].len =3D skb_headlen(skb); =20 - wqe_desc->hi_addr =3D upper_32_bits(dma_info[0].dma); - wqe_desc->lo_addr =3D lower_32_bits(dma_info[0].dma); + wqe_desc->hi_addr =3D cpu_to_le32(upper_32_bits(dma_info[0].dma)); + wqe_desc->lo_addr =3D cpu_to_le32(lower_32_bits(dma_info[0].dma)); =20 - wqe_desc->ctrl_len =3D dma_info[0].len; + wqe_desc->ctrl_len =3D cpu_to_le32(dma_info[0].len); =20 for (i =3D 0; i < skb_shinfo(skb)->nr_frags; i++) { frag =3D &(skb_shinfo(skb)->frags[i]); @@ -197,7 +197,8 @@ static int hinic3_tx_csum(struct hinic3_txq *txq, struc= t hinic3_sq_task *task, union hinic3_ip ip; u8 l4_proto; =20 - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, TUNNEL_FLAG); + task->pkt_info0 |=3D cpu_to_le32(SQ_TASK_INFO0_SET(1, + TUNNEL_FLAG)); =20 ip.hdr =3D skb_network_header(skb); if (ip.v4->version =3D=3D 4) { @@ -226,7 +227,7 @@ static int hinic3_tx_csum(struct hinic3_txq *txq, struc= t hinic3_sq_task *task, } } =20 - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, INNER_L4_EN); + task->pkt_info0 |=3D cpu_to_le32(SQ_TASK_INFO0_SET(1, INNER_L4_EN)); =20 return 1; } @@ -255,26 +256,28 @@ static void get_inner_l3_l4_type(struct sk_buff *skb,= union hinic3_ip *ip, } } =20 -static void hinic3_set_tso_info(struct hinic3_sq_task *task, u32 *queue_in= fo, +static void hinic3_set_tso_info(struct hinic3_sq_task *task, __le32 *queue= _info, enum hinic3_l4_offload_type l4_offload, u32 offset, u32 mss) { if (l4_offload =3D=3D HINIC3_L4_OFFLOAD_TCP) { - *queue_info |=3D SQ_CTRL_QUEUE_INFO_SET(1, TSO); - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, INNER_L4_EN); + *queue_info |=3D cpu_to_le32(SQ_CTRL_QUEUE_INFO_SET(1, TSO)); + task->pkt_info0 |=3D cpu_to_le32(SQ_TASK_INFO0_SET(1, + INNER_L4_EN)); } else if (l4_offload =3D=3D HINIC3_L4_OFFLOAD_UDP) { - *queue_info |=3D SQ_CTRL_QUEUE_INFO_SET(1, UFO); - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, INNER_L4_EN); + *queue_info |=3D cpu_to_le32(SQ_CTRL_QUEUE_INFO_SET(1, UFO)); + task->pkt_info0 |=3D cpu_to_le32(SQ_TASK_INFO0_SET(1, + INNER_L4_EN)); } =20 /* enable L3 calculation */ - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, INNER_L3_EN); + task->pkt_info0 |=3D cpu_to_le32(SQ_TASK_INFO0_SET(1, INNER_L3_EN)); =20 - *queue_info |=3D SQ_CTRL_QUEUE_INFO_SET(offset >> 1, PLDOFF); + *queue_info |=3D cpu_to_le32(SQ_CTRL_QUEUE_INFO_SET(offset >> 1, PLDOFF)); =20 /* set MSS value */ - *queue_info &=3D ~SQ_CTRL_QUEUE_INFO_MSS_MASK; - *queue_info |=3D SQ_CTRL_QUEUE_INFO_SET(mss, MSS); + *queue_info &=3D cpu_to_le32(~SQ_CTRL_QUEUE_INFO_MSS_MASK); + *queue_info |=3D cpu_to_le32(SQ_CTRL_QUEUE_INFO_SET(mss, MSS)); } =20 static __sum16 csum_magic(union hinic3_ip *ip, unsigned short proto) @@ -284,7 +287,7 @@ static __sum16 csum_magic(union hinic3_ip *ip, unsigned= short proto) csum_ipv6_magic(&ip->v6->saddr, &ip->v6->daddr, 0, proto, 0); } =20 -static int hinic3_tso(struct hinic3_sq_task *task, u32 *queue_info, +static int hinic3_tso(struct hinic3_sq_task *task, __le32 *queue_info, struct sk_buff *skb) { enum hinic3_l4_offload_type l4_offload; @@ -305,15 +308,17 @@ static int hinic3_tso(struct hinic3_sq_task *task, u3= 2 *queue_info, if (skb->encapsulation) { u32 gso_type =3D skb_shinfo(skb)->gso_type; /* L3 checksum is always enabled */ - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, OUT_L3_EN); - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, TUNNEL_FLAG); + task->pkt_info0 |=3D cpu_to_le32(SQ_TASK_INFO0_SET(1, OUT_L3_EN)); + task->pkt_info0 |=3D cpu_to_le32(SQ_TASK_INFO0_SET(1, + TUNNEL_FLAG)); =20 l4.hdr =3D skb_transport_header(skb); ip.hdr =3D skb_network_header(skb); =20 if (gso_type & SKB_GSO_UDP_TUNNEL_CSUM) { l4.udp->check =3D ~csum_magic(&ip, IPPROTO_UDP); - task->pkt_info0 |=3D SQ_TASK_INFO0_SET(1, OUT_L4_EN); + task->pkt_info0 |=3D + cpu_to_le32(SQ_TASK_INFO0_SET(1, OUT_L4_EN)); } =20 ip.hdr =3D skb_inner_network_header(skb); @@ -343,13 +348,14 @@ static void hinic3_set_vlan_tx_offload(struct hinic3_= sq_task *task, * 2=3Dselect TPID2 in IPSU, 3=3Dselect TPID3 in IPSU, * 4=3Dselect TPID4 in IPSU */ - task->vlan_offload =3D SQ_TASK_INFO3_SET(vlan_tag, VLAN_TAG) | - SQ_TASK_INFO3_SET(vlan_tpid, VLAN_TPID) | - SQ_TASK_INFO3_SET(1, VLAN_TAG_VALID); + task->vlan_offload =3D + cpu_to_le32(SQ_TASK_INFO3_SET(vlan_tag, VLAN_TAG) | + SQ_TASK_INFO3_SET(vlan_tpid, VLAN_TPID) | + SQ_TASK_INFO3_SET(1, VLAN_TAG_VALID)); } =20 static u32 hinic3_tx_offload(struct sk_buff *skb, struct hinic3_sq_task *t= ask, - u32 *queue_info, struct hinic3_txq *txq) + __le32 *queue_info, struct hinic3_txq *txq) { u32 offload =3D 0; int tso_cs_en; @@ -440,39 +446,41 @@ static u16 hinic3_set_wqe_combo(struct hinic3_txq *tx= q, } =20 static void hinic3_prepare_sq_ctrl(struct hinic3_sq_wqe_combo *wqe_combo, - u32 queue_info, int nr_descs, u16 owner) + __le32 queue_info, int nr_descs, u16 owner) { struct hinic3_sq_wqe_desc *wqe_desc =3D wqe_combo->ctrl_bd0; =20 if (wqe_combo->wqe_type =3D=3D SQ_WQE_COMPACT_TYPE) { wqe_desc->ctrl_len |=3D - SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) | - SQ_CTRL_SET(wqe_combo->wqe_type, EXTENDED) | - SQ_CTRL_SET(owner, OWNER); + cpu_to_le32(SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) | + SQ_CTRL_SET(wqe_combo->wqe_type, EXTENDED) | + SQ_CTRL_SET(owner, OWNER)); =20 /* compact wqe queue_info will transfer to chip */ wqe_desc->queue_info =3D 0; return; } =20 - wqe_desc->ctrl_len |=3D SQ_CTRL_SET(nr_descs, BUFDESC_NUM) | - SQ_CTRL_SET(wqe_combo->task_type, TASKSECT_LEN) | - SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) | - SQ_CTRL_SET(wqe_combo->wqe_type, EXTENDED) | - SQ_CTRL_SET(owner, OWNER); + wqe_desc->ctrl_len |=3D + cpu_to_le32(SQ_CTRL_SET(nr_descs, BUFDESC_NUM) | + SQ_CTRL_SET(wqe_combo->task_type, TASKSECT_LEN) | + SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) | + SQ_CTRL_SET(wqe_combo->wqe_type, EXTENDED) | + SQ_CTRL_SET(owner, OWNER)); =20 wqe_desc->queue_info =3D queue_info; - wqe_desc->queue_info |=3D SQ_CTRL_QUEUE_INFO_SET(1, UC); + wqe_desc->queue_info |=3D cpu_to_le32(SQ_CTRL_QUEUE_INFO_SET(1, UC)); =20 if (!SQ_CTRL_QUEUE_INFO_GET(wqe_desc->queue_info, MSS)) { wqe_desc->queue_info |=3D - SQ_CTRL_QUEUE_INFO_SET(HINIC3_TX_MSS_DEFAULT, MSS); + cpu_to_le32(SQ_CTRL_QUEUE_INFO_SET(HINIC3_TX_MSS_DEFAULT, MSS)); } else if (SQ_CTRL_QUEUE_INFO_GET(wqe_desc->queue_info, MSS) < HINIC3_TX_MSS_MIN) { /* mss should not be less than 80 */ - wqe_desc->queue_info &=3D ~SQ_CTRL_QUEUE_INFO_MSS_MASK; + wqe_desc->queue_info &=3D + cpu_to_le32(~SQ_CTRL_QUEUE_INFO_MSS_MASK); wqe_desc->queue_info |=3D - SQ_CTRL_QUEUE_INFO_SET(HINIC3_TX_MSS_MIN, MSS); + cpu_to_le32(SQ_CTRL_QUEUE_INFO_SET(HINIC3_TX_MSS_MIN, MSS)); } } =20 @@ -482,12 +490,13 @@ static netdev_tx_t hinic3_send_one_skb(struct sk_buff= *skb, { struct hinic3_sq_wqe_combo wqe_combo =3D {}; struct hinic3_tx_info *tx_info; - u32 offload, queue_info =3D 0; struct hinic3_sq_task task; u16 wqebb_cnt, num_sge; + __le32 queue_info =3D 0; u16 saved_wq_prod_idx; u16 owner, pi =3D 0; u8 saved_sq_owner; + u32 offload; int err; =20 if (unlikely(skb->len < MIN_SKB_LEN)) { diff --git a/drivers/net/ethernet/huawei/hinic3/hinic3_tx.h b/drivers/net/e= thernet/huawei/hinic3/hinic3_tx.h index 9e505cc19dd5..21dfe879a29a 100644 --- a/drivers/net/ethernet/huawei/hinic3/hinic3_tx.h +++ b/drivers/net/ethernet/huawei/hinic3/hinic3_tx.h @@ -58,7 +58,7 @@ enum hinic3_tx_offload_type { #define SQ_CTRL_QUEUE_INFO_SET(val, member) \ FIELD_PREP(SQ_CTRL_QUEUE_INFO_##member##_MASK, val) #define SQ_CTRL_QUEUE_INFO_GET(val, member) \ - FIELD_GET(SQ_CTRL_QUEUE_INFO_##member##_MASK, val) + FIELD_GET(SQ_CTRL_QUEUE_INFO_##member##_MASK, le32_to_cpu(val)) =20 #define SQ_CTRL_MAX_PLDOFF 221 =20 @@ -77,17 +77,17 @@ enum hinic3_tx_offload_type { FIELD_PREP(SQ_TASK_INFO3_##member##_MASK, val) =20 struct hinic3_sq_wqe_desc { - u32 ctrl_len; - u32 queue_info; - u32 hi_addr; - u32 lo_addr; + __le32 ctrl_len; + __le32 queue_info; + __le32 hi_addr; + __le32 lo_addr; }; =20 struct hinic3_sq_task { - u32 pkt_info0; - u32 ip_identify; - u32 rsvd; - u32 vlan_offload; + __le32 pkt_info0; + __le32 ip_identify; + __le32 rsvd; + __le32 vlan_offload; }; =20 struct hinic3_sq_wqe_combo { --=20 2.43.0