From nobody Sun Feb 8 14:11:08 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3A1123A9A8; Sun, 1 Feb 2026 03:42:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769917328; cv=none; b=jGZk9XgV2YDuQ7rHvlosKR6nvIy3TSRbJES0SvKT+DLTFPa1az3aJHIjLbpw9yu+2TXzdk0B3EdkNpIMLNwy2xMscfZR5PYkHZKU375cwZYzcNySXrfYxM1eAqA53luOiLq86CUvCC5u1rYYUdeI/gslXL2wRZztwPibpqxESJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769917328; c=relaxed/simple; bh=q1yqherTZ1VwTP5irNF4KDqWVxAHd1f324KoOIjrlh8=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=dZRsiiIqCgyxpg43jDvhv7s9IMSdmHOw617JhroyoS8D2sw2LdRg9i5d7gWAxShnB1PF1D55fiCdCpHAnVHnSN/MSzU/A5Q50DsxZudmQs3tBdtumw0O5iKdNH9p7sbaMtmX+M6WQA+QAbzGj9lm6g/9LxjQyNf7PSsRXL9tnxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vmOLb-000000002Wu-1HSD; Sun, 01 Feb 2026 03:42:03 +0000 Date: Sun, 1 Feb 2026 03:42:00 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v3 2/3] net: dsa: mxl-gsw1xx: configure SerDes port polarities Message-ID: <8bf79b3476e23673fceffbe2bc9d6abc13d132e5.1769916962.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Configure SerDes (port 4) RX and TX polarities using the newly introduced generic properties. The polarities are described at the port level which equals the polarities of the external pins of the chip. Note that the RX lane is inverted internally and the vendor driver simply always sets bit GSW1XX_SGMII_PHY_RX0_CFG2_INVERT unconditionally to end up with the correct (ie. as documented in datasheets) polarity at the external pins. In this sense, PHY_POLARITY_NORMAL denotes normal polarity for pins as documented for the MRQFN 105-pin package (GSW120, GSW125, GSW140, GSW141 and GSW145 all use the same package and have identical pin layouts except for TP port 2 and 3 being N/C on GSW12x): pin B18 (TX0_P) positive signal of the differential SGMII data output pair pin B19 (TX0_M) negative signal of the differential SGMII data output pair pin B20 (RX0_P) positive signal of the differential SGMII data input pair pin B21 (RX0_M) negative signal of the differential SGMII data input pair Signed-off-by: Daniel Golle --- v3: be clear about describing polarity at external pins v2: use phy_get_manual_rx_polarity and phy_get_manual_tx_polarity --- drivers/net/dsa/lantiq/Kconfig | 1 + drivers/net/dsa/lantiq/mxl-gsw1xx.c | 39 +++++++++++++++++++++-------- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/net/dsa/lantiq/Kconfig b/drivers/net/dsa/lantiq/Kconfig index bad13817af25..98efeef2661b 100644 --- a/drivers/net/dsa/lantiq/Kconfig +++ b/drivers/net/dsa/lantiq/Kconfig @@ -15,6 +15,7 @@ config NET_DSA_MXL_GSW1XX tristate "MaxLinear GSW1xx Ethernet switch support" select NET_DSA_TAG_MXL_GSW1XX select NET_DSA_LANTIQ_COMMON + select PHY_COMMON_PROPS help This enables support for the Intel/MaxLinear GSW1xx family of 1GE switches. diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index 79cf72cc77be..61220b5fe5af 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include #include @@ -229,11 +231,17 @@ static int gsw1xx_pcs_phy_xaui_write(struct gsw1xx_pr= iv *priv, u16 addr, 1000, 100000); } =20 -static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) +static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv, phy_interface_t inte= rface) { + struct dsa_port *sgmii_port; + unsigned int pol; int ret; u16 val; =20 + sgmii_port =3D dsa_to_port(priv->gswip.ds, GSW1XX_SGMII_PORT); + if (!sgmii_port) + return -EINVAL; + /* Assert and deassert SGMII shell reset */ ret =3D regmap_set_bits(priv->shell, GSW1XX_SHELL_RST_REQ, GSW1XX_RST_REQ_SGMII_SHELL); @@ -260,15 +268,20 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT, GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF); =20 + ret =3D phy_get_manual_rx_polarity(of_fwnode_handle(sgmii_port->dn), + phy_modes(interface), &pol); + if (ret) + return ret; + /* RX lane seems to be inverted internally, so bit * GSW1XX_SGMII_PHY_RX0_CFG2_INVERT needs to be set for normal - * (ie. non-inverted) operation. - * - * TODO: Take care of inverted RX pair once generic property is - * available + * (ie. non-inverted) operation matching the chips external pins as + * described in datasheets dated 2023-11-08, ie. pin B20 (RX0_P) being + * the positive signal and pin B21 (RX0_M) being the negative signal of + * the differential input pair. */ - - val |=3D GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; + if (pol =3D=3D PHY_POL_NORMAL) + val |=3D GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; =20 ret =3D regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val); if (ret < 0) @@ -277,9 +290,13 @@ static int gsw1xx_pcs_reset(struct gsw1xx_priv *priv) val =3D FIELD_PREP(GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL, GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF); =20 - /* TODO: Take care of inverted TX pair once generic property is - * available - */ + ret =3D phy_get_manual_tx_polarity(of_fwnode_handle(sgmii_port->dn), + phy_modes(interface), &pol); + if (ret) + return ret; + + if (pol =3D=3D PHY_POL_INVERT) + val |=3D GSW1XX_SGMII_PHY_TX0_CFG3_INVERT; =20 ret =3D regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_TX0_CFG3, val); if (ret < 0) @@ -336,7 +353,7 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, u= nsigned int neg_mode, priv->tbi_interface =3D PHY_INTERFACE_MODE_NA; =20 if (!reconf) - ret =3D gsw1xx_pcs_reset(priv); + ret =3D gsw1xx_pcs_reset(priv, interface); =20 if (ret) return ret; --=20 2.52.0