From nobody Tue Oct 7 11:52:38 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3B052FEE0B; Thu, 10 Jul 2025 20:07:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178074; cv=none; b=cQ7nZv3ggvX78THuQ0tw+bjQPh/yoyl+RoP4m1Q0AbbMw1fNiIAAmVG4POKLqXdUAZ2wsUvsPUiLibKc0MyGfobaydH99/Kv2FTgfYzVjRLbAEEqBYUF/EVx/7YfwHXMqSkr9ax+ee8wVuCc91pav+TgFuwFWeT29OOX6OOVB28= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178074; c=relaxed/simple; bh=zEqi+e0G8dOBszsOgdaKCLuTl0I6AIiT1HKDYaGg9vY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Vd+5yIglxvkcPCalUFu7hmYA8rExwsi5aPVQ+D9dlD7D5tcCQZeTgmxWXrmjZQO6I9ovOVeJE2F7f2jiLEeHPqDKABv8sJHOie3SYLJTQNm/zpXIl/ujwUinlT3/xgBFAMiAY7IDPIcl2p3PiRHbfkloDdjuLIVyYS38HpI6hsI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=zfstdgp6; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="zfstdgp6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1752178072; x=1783714072; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zEqi+e0G8dOBszsOgdaKCLuTl0I6AIiT1HKDYaGg9vY=; b=zfstdgp6SsWpu0Onv8xncPuL9Ot0aGckhNmmkb5Mr4ZwR0k64Yh+RDJh 8jbpjRsVpin2g9B+Z3q694AmU7EoJclqH/latFhOYmL7LxnDIrMoF/NxH s4Lm8ABUJBCg6J0lpaMYP4ex1VH4xbbs2TtbVeeRRpKK/N8fTCZROw0vi hOGWMbRUWNlH0mq9xThvqaR3brvOVIFopZqRcYN7OyFJ7VIZgEPizJh5R /v3MS2u+gC1LtjtrPFkFNpHlH20bkW+uTtIOWTobdG7D8KUVRx20upnST FZmokOgZLMtbS525dl8W0llvC3m1fNCV1hcT1rLJGG9EPiCJhRtBoQ7dC g==; X-CSE-ConnectionGUID: qOQSLemoQZOGUxBCHa7nXg== X-CSE-MsgGUID: xBxAMcQRRHCS1hMQCO6lXQ== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="275215682" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:33 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:33 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 24/32] clk: at91: sama5d3: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:07:17 -0700 Message-ID: <8b9b4447d93f048bc95ab083c9fbe1d5ccd8acd1.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch SAMA5D3 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama5d3.c | 122 +++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 59 deletions(-) diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 8326bb6a291c..e5b061783b09 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d3_pcr_layout =3D= { .div_mask =3D GENMASK(17, 16), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sama5d3_systemck[] =3D { @@ -47,14 +47,14 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, }; =20 static const struct { @@ -114,24 +114,15 @@ static const struct { =20 static void __init sama5d3_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_hw *smdck_hw, *usbck_hw, *hw; + struct clk_parent_data parent_data[5]; struct pmc_data *sama5d3_pmc; - const char *parent_names[5]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -143,54 +134,55 @@ static void __init sama5d3_pmc_setup(struct device_no= de *np) if (!sama5d3_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + mainck_hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, paren= t_data, 2); + if (IS_ERR(mainck_hw)) goto err_free; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, &AT91_CLK_PD_HW(main= ck_hw), 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d3_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, &AT91_CLK_PD_= HW(mainck_hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d3_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -199,28 +191,30 @@ static void __init sama5d3_pmc_setup(struct device_no= de *np) =20 sama5d3_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, NULL, = 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_d= ata, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]); for (i =3D 0; i < 3; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -229,9 +223,18 @@ static void __init sama5d3_pmc_setup(struct device_nod= e *np) sama5d3_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sama5d3_systemck[0].parent_hw =3D sama5d3_pmc->chws[PMC_MCK]; + sama5d3_systemck[1].parent_hw =3D sama5d3_pmc->chws[PMC_MCK]; + sama5d3_systemck[2].parent_hw =3D smdck_hw; + sama5d3_systemck[3].parent_hw =3D usbck_hw; + sama5d3_systemck[4].parent_hw =3D usbck_hw; + sama5d3_systemck[5].parent_hw =3D sama5d3_pmc->pchws[0]; + sama5d3_systemck[6].parent_hw =3D sama5d3_pmc->pchws[1]; + sama5d3_systemck[7].parent_hw =3D sama5d3_pmc->pchws[2]; for (i =3D 0; i < ARRAY_SIZE(sama5d3_systemck); i++) { - hw =3D at91_clk_register_system(regmap, sama5d3_systemck[i].n, - sama5d3_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, sama5d3_systemck[i].n, NULL, + &AT91_CLK_PD_HW(sama5d3_systemck[i].parent_hw), sama5d3_systemck[i].id, sama5d3_systemck[i].flags); if (IS_ERR(hw)) @@ -244,7 +247,8 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d3_pcr_layout, sama5d3_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]), sama5d3_periphck[i].id, &sama5d3_periphck[i].r, INT_MIN, --=20 2.43.0