From nobody Tue Dec 16 05:41:16 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC5B0E92FFD for ; Sat, 7 Oct 2023 07:57:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343762AbjJGH51 (ORCPT ); Sat, 7 Oct 2023 03:57:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343754AbjJGH5Z (ORCPT ); Sat, 7 Oct 2023 03:57:25 -0400 Received: from mail-oo1-xc34.google.com (mail-oo1-xc34.google.com [IPv6:2607:f8b0:4864:20::c34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96D18BF; Sat, 7 Oct 2023 00:57:19 -0700 (PDT) Received: by mail-oo1-xc34.google.com with SMTP id 006d021491bc7-57bce354d94so1477293eaf.2; Sat, 07 Oct 2023 00:57:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696665439; x=1697270239; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DfspLLpV5SZPNKsa50ONpV2XPtgK81hq6ZHklRUaa0U=; b=lLy2J5BHJ91bUKYr3tmL2Xhz4TUnkTbPU55gr7LvoKVZWOBphlhbTSz7irjrbzpfG/ ekLmKWxuxY+RO/ydE8wUAvqaQ4Vcs1kae9UojH7vn1T7B8PJjY+6FT7hddkxl5ELj9Rt k3tcyZEE7s5rK3iOHe+m/nZbuCaE9Nl4BeojAIbhVd9OlUwT5NNsI8SEPAFCuPIaaOpq CDEL1Sr6wxNn6briYydLYCUXvXxacj7KiCTtfH6ZA/rHFv/2MWnd9OnESMGuXKaZLTri o8ceDCLWBOeKQw5ot+HCGI20ygLbEMZa7AgEC9WbIiiUHNyniEKfZc5mIw6NFh4OAsAL 5X1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696665439; x=1697270239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DfspLLpV5SZPNKsa50ONpV2XPtgK81hq6ZHklRUaa0U=; b=UCI/o8S3wQCectnY5eILWKYItt0M17vZR4GQg8ReinFYwcYCMfrfB1CwwOmkXQcsRq 0+tveTzuk2U7mb7SzPBFUHbD6m6OLssiKOSZjDagHrlpitlaQKyjkXQq1e9TWzvARcjZ bBB+N4agRDWvo0Uy/k5blj2MqlhjYcOq0JzEGOHZ9mkYwyGJldAZI6FJYt9CN1gYD4/e OqrabXBeD1x7iMLPZWbQn+rSQxU7kIi3nQsZ0RpvBdQ90lVypl/0kDuxYUMSMlMsGbpA ar4R6mpx5B4IwSsTAQdW/d8xADJ5C4MuOkL73Qy6qe8vMprX/dBd6n506dwl1lewkjOs NAXg== X-Gm-Message-State: AOJu0YxzM7tPMO+ssBFK5OOMj2HTSlEUAUiF6TEOjefQmgb/wn24Zna6 TxTbwoekwxgUIgSpVvI9gv4= X-Google-Smtp-Source: AGHT+IHattVhSb60ASeajsQAMCaTOmsmuNHNq2cZn96PGO3n8TcMm3g2UyTY76Kq8NJ+vG9momThiQ== X-Received: by 2002:a05:6870:7192:b0:196:45b7:9385 with SMTP id d18-20020a056870719200b0019645b79385mr11045434oah.27.1696665438272; Sat, 07 Oct 2023 00:57:18 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id eg46-20020a05687098ae00b001e193298739sm1101724oab.3.2023.10.07.00.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Oct 2023 00:57:17 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Inochi Amaoto , Conor Dooley Subject: [PATCH v5 08/10] riscv: dts: add initial Sophgo SG2042 SoC device tree Date: Sat, 7 Oct 2023 15:57:10 +0800 Message-Id: <8a5f5a98a289fb94e23347ac5b19f8aa70093855.1696663037.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen Wang Milk-V Pioneer motherboard is powered by SG2042. SG2042 is server grade chip with high performance, low power consumption and high data throughput. Key features: - 64 RISC-V cpu cores - 4 cores per cluster, 16 clusters on chip - More info is available at [1]. Currently only support booting into console with only uart, other features will be added soon later. Reviewed-by: Guo Ren Acked-by: Chao Wei Co-developed-by: Xiaoguang Xing Signed-off-by: Xiaoguang Xing Co-developed-by: Inochi Amaoto Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++ 3 files changed, 2326 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 97cb8abcfeee..fedf042e5fb4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES M: Chao Wei M: Chen Wang S: Maintained +F: arch/riscv/boot/dts/sophgo/ F: Documentation/devicetree/bindings/riscv/sophgo.yaml =20 SOUND diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/= dts/sophgo/sg2042-cpus.dtsi new file mode 100644 index 000000000000..b136b6c4128c --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -0,0 +1,2000 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <50000000>; + + cpu-map { + socket0 { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + core1 { + cpu =3D <&cpu5>; + }; + core2 { + cpu =3D <&cpu6>; + }; + core3 { + cpu =3D <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu16>; + }; + core1 { + cpu =3D <&cpu17>; + }; + core2 { + cpu =3D <&cpu18>; + }; + core3 { + cpu =3D <&cpu19>; + }; + }; + + cluster3 { + core0 { + cpu =3D <&cpu20>; + }; + core1 { + cpu =3D <&cpu21>; + }; + core2 { + cpu =3D <&cpu22>; + }; + core3 { + cpu =3D <&cpu23>; + }; + }; + + cluster4 { + core0 { + cpu =3D <&cpu8>; + }; + core1 { + cpu =3D <&cpu9>; + }; + core2 { + cpu =3D <&cpu10>; + }; + core3 { + cpu =3D <&cpu11>; + }; + }; + + cluster5 { + core0 { + cpu =3D <&cpu12>; + }; + core1 { + cpu =3D <&cpu13>; + }; + core2 { + cpu =3D <&cpu14>; + }; + core3 { + cpu =3D <&cpu15>; + }; + }; + + cluster6 { + core0 { + cpu =3D <&cpu24>; + }; + core1 { + cpu =3D <&cpu25>; + }; + core2 { + cpu =3D <&cpu26>; + }; + core3 { + cpu =3D <&cpu27>; + }; + }; + + cluster7 { + core0 { + cpu =3D <&cpu28>; + }; + core1 { + cpu =3D <&cpu29>; + }; + core2 { + cpu =3D <&cpu30>; + }; + core3 { + cpu =3D <&cpu31>; + }; + }; + + cluster8 { + core0 { + cpu =3D <&cpu32>; + }; + core1 { + cpu =3D <&cpu33>; + }; + core2 { + cpu =3D <&cpu34>; + }; + core3 { + cpu =3D <&cpu35>; + }; + }; + + cluster9 { + core0 { + cpu =3D <&cpu36>; + }; + core1 { + cpu =3D <&cpu37>; + }; + core2 { + cpu =3D <&cpu38>; + }; + core3 { + cpu =3D <&cpu39>; + }; + }; + + cluster10 { + core0 { + cpu =3D <&cpu48>; + }; + core1 { + cpu =3D <&cpu49>; + }; + core2 { + cpu =3D <&cpu50>; + }; + core3 { + cpu =3D <&cpu51>; + }; + }; + + cluster11 { + core0 { + cpu =3D <&cpu52>; + }; + core1 { + cpu =3D <&cpu53>; + }; + core2 { + cpu =3D <&cpu54>; + }; + core3 { + cpu =3D <&cpu55>; + }; + }; + + cluster12 { + core0 { + cpu =3D <&cpu40>; + }; + core1 { + cpu =3D <&cpu41>; + }; + core2 { + cpu =3D <&cpu42>; + }; + core3 { + cpu =3D <&cpu43>; + }; + }; + + cluster13 { + core0 { + cpu =3D <&cpu44>; + }; + core1 { + cpu =3D <&cpu45>; + }; + core2 { + cpu =3D <&cpu46>; + }; + core3 { + cpu =3D <&cpu47>; + }; + }; + + cluster14 { + core0 { + cpu =3D <&cpu56>; + }; + core1 { + cpu =3D <&cpu57>; + }; + core2 { + cpu =3D <&cpu58>; + }; + core3 { + cpu =3D <&cpu59>; + }; + }; + + cluster15 { + core0 { + cpu =3D <&cpu60>; + }; + core1 { + cpu =3D <&cpu61>; + }; + core2 { + cpu =3D <&cpu62>; + }; + core3 { + cpu =3D <&cpu63>; + }; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <0>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <1>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <2>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <3>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu4: cpu@4 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <4>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu5: cpu@5 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <5>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu6: cpu@6 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <6>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu7: cpu@7 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <7>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu8: cpu@8 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <8>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu8_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu9: cpu@9 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <9>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu9_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu10: cpu@10 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <10>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu10_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu11: cpu@11 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <11>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu11_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu12: cpu@12 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <12>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu12_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu13: cpu@13 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <13>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu13_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu14: cpu@14 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <14>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu14_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu15: cpu@15 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <15>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu15_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu16: cpu@16 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <16>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu16_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu17: cpu@17 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <17>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu17_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu18: cpu@18 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <18>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu18_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu19: cpu@19 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <19>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu19_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu20: cpu@20 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <20>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu20_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu21: cpu@21 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <21>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu21_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu22: cpu@22 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <22>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu22_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu23: cpu@23 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <23>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu23_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu24: cpu@24 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <24>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu24_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu25: cpu@25 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <25>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu25_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu26: cpu@26 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <26>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu26_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu27: cpu@27 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <27>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu27_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu28: cpu@28 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <28>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu28_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu29: cpu@29 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <29>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu29_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu30: cpu@30 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <30>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu30_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu31: cpu@31 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <31>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu31_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu32: cpu@32 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <32>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu32_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu33: cpu@33 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <33>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu33_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu34: cpu@34 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <34>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu34_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu35: cpu@35 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <35>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu35_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu36: cpu@36 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <36>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu36_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu37: cpu@37 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <37>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu37_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu38: cpu@38 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <38>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu38_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu39: cpu@39 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <39>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu39_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu40: cpu@40 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <40>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu40_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu41: cpu@41 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <41>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu41_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu42: cpu@42 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <42>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu42_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu43: cpu@43 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <43>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu43_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu44: cpu@44 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <44>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu44_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu45: cpu@45 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <45>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu45_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu46: cpu@46 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <46>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu46_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu47: cpu@47 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <47>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu47_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu48: cpu@48 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <48>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu48_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu49: cpu@49 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <49>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu49_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu50: cpu@50 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <50>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu50_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu51: cpu@51 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <51>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu51_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu52: cpu@52 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <52>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu52_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu53: cpu@53 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <53>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu53_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu54: cpu@54 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <54>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu54_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu55: cpu@55 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <55>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu55_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu56: cpu@56 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <56>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu56_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu57: cpu@57 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <57>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu57_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu58: cpu@58 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <58>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu58_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu59: cpu@59 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <59>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu59_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu60: cpu@60 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <60>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu60_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu61: cpu@61 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <61>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu61_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu62: cpu@62 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <62>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu62_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu63: cpu@63 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <63>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu63_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + l2_cache0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache2: cache-controller-2 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache3: cache-controller-3 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache4: cache-controller-4 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache5: cache-controller-5 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache6: cache-controller-6 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache7: cache-controller-7 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache8: cache-controller-8 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache9: cache-controller-9 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache10: cache-controller-10 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache11: cache-controller-11 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache12: cache-controller-12 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache13: cache-controller-13 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache14: cache-controller-14 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache15: cache-controller-15 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi new file mode 100644 index 000000000000..93256540d078 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/dts-v1/; +#include + +#include "sg2042-cpus.dtsi" + +/ { + compatible =3D "sophgo,sg2042"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + + aliases { + serial0 =3D &uart0; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint_mswi: interrupt-controller@7094000000 { + compatible =3D "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; + reg =3D <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended =3D <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>, + <&cpu4_intc 3>, + <&cpu5_intc 3>, + <&cpu6_intc 3>, + <&cpu7_intc 3>, + <&cpu8_intc 3>, + <&cpu9_intc 3>, + <&cpu10_intc 3>, + <&cpu11_intc 3>, + <&cpu12_intc 3>, + <&cpu13_intc 3>, + <&cpu14_intc 3>, + <&cpu15_intc 3>, + <&cpu16_intc 3>, + <&cpu17_intc 3>, + <&cpu18_intc 3>, + <&cpu19_intc 3>, + <&cpu20_intc 3>, + <&cpu21_intc 3>, + <&cpu22_intc 3>, + <&cpu23_intc 3>, + <&cpu24_intc 3>, + <&cpu25_intc 3>, + <&cpu26_intc 3>, + <&cpu27_intc 3>, + <&cpu28_intc 3>, + <&cpu29_intc 3>, + <&cpu30_intc 3>, + <&cpu31_intc 3>, + <&cpu32_intc 3>, + <&cpu33_intc 3>, + <&cpu34_intc 3>, + <&cpu35_intc 3>, + <&cpu36_intc 3>, + <&cpu37_intc 3>, + <&cpu38_intc 3>, + <&cpu39_intc 3>, + <&cpu40_intc 3>, + <&cpu41_intc 3>, + <&cpu42_intc 3>, + <&cpu43_intc 3>, + <&cpu44_intc 3>, + <&cpu45_intc 3>, + <&cpu46_intc 3>, + <&cpu47_intc 3>, + <&cpu48_intc 3>, + <&cpu49_intc 3>, + <&cpu50_intc 3>, + <&cpu51_intc 3>, + <&cpu52_intc 3>, + <&cpu53_intc 3>, + <&cpu54_intc 3>, + <&cpu55_intc 3>, + <&cpu56_intc 3>, + <&cpu57_intc 3>, + <&cpu58_intc 3>, + <&cpu59_intc 3>, + <&cpu60_intc 3>, + <&cpu61_intc 3>, + <&cpu62_intc 3>, + <&cpu63_intc 3>; + }; + + clint_mtimer0: timer@70ac000000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac000000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + clint_mtimer1: timer@70ac010000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac010000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu4_intc 7>, + <&cpu5_intc 7>, + <&cpu6_intc 7>, + <&cpu7_intc 7>; + }; + + clint_mtimer2: timer@70ac020000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac020000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu8_intc 7>, + <&cpu9_intc 7>, + <&cpu10_intc 7>, + <&cpu11_intc 7>; + }; + + clint_mtimer3: timer@70ac030000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac030000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu12_intc 7>, + <&cpu13_intc 7>, + <&cpu14_intc 7>, + <&cpu15_intc 7>; + }; + + clint_mtimer4: timer@70ac040000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac040000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu16_intc 7>, + <&cpu17_intc 7>, + <&cpu18_intc 7>, + <&cpu19_intc 7>; + }; + + clint_mtimer5: timer@70ac050000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac050000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu20_intc 7>, + <&cpu21_intc 7>, + <&cpu22_intc 7>, + <&cpu23_intc 7>; + }; + + clint_mtimer6: timer@70ac060000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac060000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu24_intc 7>, + <&cpu25_intc 7>, + <&cpu26_intc 7>, + <&cpu27_intc 7>; + }; + + clint_mtimer7: timer@70ac070000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac070000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu28_intc 7>, + <&cpu29_intc 7>, + <&cpu30_intc 7>, + <&cpu31_intc 7>; + }; + + clint_mtimer8: timer@70ac080000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac080000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu32_intc 7>, + <&cpu33_intc 7>, + <&cpu34_intc 7>, + <&cpu35_intc 7>; + }; + + clint_mtimer9: timer@70ac090000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac090000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu36_intc 7>, + <&cpu37_intc 7>, + <&cpu38_intc 7>, + <&cpu39_intc 7>; + }; + + clint_mtimer10: timer@70ac0a0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu40_intc 7>, + <&cpu41_intc 7>, + <&cpu42_intc 7>, + <&cpu43_intc 7>; + }; + + clint_mtimer11: timer@70ac0b0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu44_intc 7>, + <&cpu45_intc 7>, + <&cpu46_intc 7>, + <&cpu47_intc 7>; + }; + + clint_mtimer12: timer@70ac0c0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu48_intc 7>, + <&cpu49_intc 7>, + <&cpu50_intc 7>, + <&cpu51_intc 7>; + }; + + clint_mtimer13: timer@70ac0d0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu52_intc 7>, + <&cpu53_intc 7>, + <&cpu54_intc 7>, + <&cpu55_intc 7>; + }; + + clint_mtimer14: timer@70ac0e0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu56_intc 7>, + <&cpu57_intc 7>, + <&cpu58_intc 7>, + <&cpu59_intc 7>; + }; + + clint_mtimer15: timer@70ac0f0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu60_intc 7>, + <&cpu61_intc 7>, + <&cpu62_intc 7>, + <&cpu63_intc 7>; + }; + + intc: interrupt-controller@7090000000 { + compatible =3D "sophgo,sg2042-plic", "thead,c900-plic"; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + reg =3D <0x00000070 0x90000000 0x00000000 0x04000000>; + interrupt-controller; + interrupts-extended =3D + <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>, + <&cpu8_intc 11>, <&cpu8_intc 9>, + <&cpu9_intc 11>, <&cpu9_intc 9>, + <&cpu10_intc 11>, <&cpu10_intc 9>, + <&cpu11_intc 11>, <&cpu11_intc 9>, + <&cpu12_intc 11>, <&cpu12_intc 9>, + <&cpu13_intc 11>, <&cpu13_intc 9>, + <&cpu14_intc 11>, <&cpu14_intc 9>, + <&cpu15_intc 11>, <&cpu15_intc 9>, + <&cpu16_intc 11>, <&cpu16_intc 9>, + <&cpu17_intc 11>, <&cpu17_intc 9>, + <&cpu18_intc 11>, <&cpu18_intc 9>, + <&cpu19_intc 11>, <&cpu19_intc 9>, + <&cpu20_intc 11>, <&cpu20_intc 9>, + <&cpu21_intc 11>, <&cpu21_intc 9>, + <&cpu22_intc 11>, <&cpu22_intc 9>, + <&cpu23_intc 11>, <&cpu23_intc 9>, + <&cpu24_intc 11>, <&cpu24_intc 9>, + <&cpu25_intc 11>, <&cpu25_intc 9>, + <&cpu26_intc 11>, <&cpu26_intc 9>, + <&cpu27_intc 11>, <&cpu27_intc 9>, + <&cpu28_intc 11>, <&cpu28_intc 9>, + <&cpu29_intc 11>, <&cpu29_intc 9>, + <&cpu30_intc 11>, <&cpu30_intc 9>, + <&cpu31_intc 11>, <&cpu31_intc 9>, + <&cpu32_intc 11>, <&cpu32_intc 9>, + <&cpu33_intc 11>, <&cpu33_intc 9>, + <&cpu34_intc 11>, <&cpu34_intc 9>, + <&cpu35_intc 11>, <&cpu35_intc 9>, + <&cpu36_intc 11>, <&cpu36_intc 9>, + <&cpu37_intc 11>, <&cpu37_intc 9>, + <&cpu38_intc 11>, <&cpu38_intc 9>, + <&cpu39_intc 11>, <&cpu39_intc 9>, + <&cpu40_intc 11>, <&cpu40_intc 9>, + <&cpu41_intc 11>, <&cpu41_intc 9>, + <&cpu42_intc 11>, <&cpu42_intc 9>, + <&cpu43_intc 11>, <&cpu43_intc 9>, + <&cpu44_intc 11>, <&cpu44_intc 9>, + <&cpu45_intc 11>, <&cpu45_intc 9>, + <&cpu46_intc 11>, <&cpu46_intc 9>, + <&cpu47_intc 11>, <&cpu47_intc 9>, + <&cpu48_intc 11>, <&cpu48_intc 9>, + <&cpu49_intc 11>, <&cpu49_intc 9>, + <&cpu50_intc 11>, <&cpu50_intc 9>, + <&cpu51_intc 11>, <&cpu51_intc 9>, + <&cpu52_intc 11>, <&cpu52_intc 9>, + <&cpu53_intc 11>, <&cpu53_intc 9>, + <&cpu54_intc 11>, <&cpu54_intc 9>, + <&cpu55_intc 11>, <&cpu55_intc 9>, + <&cpu56_intc 11>, <&cpu56_intc 9>, + <&cpu57_intc 11>, <&cpu57_intc 9>, + <&cpu58_intc 11>, <&cpu58_intc 9>, + <&cpu59_intc 11>, <&cpu59_intc 9>, + <&cpu60_intc 11>, <&cpu60_intc 9>, + <&cpu61_intc 11>, <&cpu61_intc 9>, + <&cpu62_intc 11>, <&cpu62_intc 9>, + <&cpu63_intc 11>, <&cpu63_intc 9>; + riscv,ndev =3D <224>; + }; + + uart0: serial@7040000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x00000070 0x40000000 0x00000000 0x00001000>; + interrupt-parent =3D <&intc>; + interrupts =3D <112 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency =3D <500000000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1