From nobody Thu Apr 2 06:28:48 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C6F53ED5A2; Thu, 5 Mar 2026 17:44:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732681; cv=none; b=t6mCq7mdRaiiLNlR0P+OJHzTv4sLUOoxQUVQJCWeJKQV96TOiu8z8g8T52/t+mwZQ837OHgmY0I7AHC6kobugLbQ0xop2RON5YJeF+rENNBWiKb+yP3H9gq1YeyWRFBA8oQS3I4kIytnFvyqSIa9ZfchkM8ny6lq2M+mbPZMeIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732681; c=relaxed/simple; bh=1Opn2f6DMZ4y5pqtubhiSso/f/rsTDueXc5LKTv0leM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d6S0dhEkJVz6gC80aIc8clq+004MwUXLJP9NsLCBMYndozAeF1s9mklIrNS3KjkztJmju1e8C1fCnjR570adSyFHrCluY11jsb/QEnn/1RlC7Ylsl2eqEe9dnj9JWmd9ClsKMPt5bhbVycspCIKBE2E6XGY2sEJ8hJntgSMm4EU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QKlvR77e; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QKlvR77e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772732680; x=1804268680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Opn2f6DMZ4y5pqtubhiSso/f/rsTDueXc5LKTv0leM=; b=QKlvR77eTZsPdyfW2pGJCHLhg5z8ZFArhigcDobeW+Lw3gU4mQ+e0OSs V0L7KTyvlNVa5LUg7kdWh/zMH9TNHmtxqOaNVrAvbP2lHq09EVPVnRbN3 WDQ5AFOrcJr/iO6cePBLctsWb7wAS2DK3j8axh5mX/BJeAFOEIPPmC1fw os32vGV43HvQI6exeOPss1d2LikDz+Hu67cM849f1X7Kf3yUStOBFNCpn 0xdIYYpMhQEldRyWXq7CC/jjlKJakKAlOo3rJswgNESrQV9x6jVuHMlDC grcDOSAoIHVaVEg2H8oQ9+mL1CSJfAF13H3UDRFtz0UjTi7GkeQ21AYvR A==; X-CSE-ConnectionGUID: oN2f2LVCTlu1UqpkC7EylQ== X-CSE-MsgGUID: u2E2VtbSSh6XQi/FVKgQ6Q== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="77431578" X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="77431578" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:38 -0800 X-CSE-ConnectionGUID: lof77IP7TMCxsd1noR2VXA== X-CSE-MsgGUID: fS3eNfvcRkKBphd1MRG0OQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="223447882" Received: from mdroper-mobl2.amr.corp.intel.com (HELO localhost) ([10.124.220.244]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:37 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , Sean Christopherson , linux-kernel@vger.kernel.org Subject: [PATCH v2 13/36] KVM: nVMX: Update intercept on TSC deadline MSR Date: Thu, 5 Mar 2026 09:43:53 -0800 Message-ID: <8987d935f9531f4afebccc6bb9d330fdb4812d80.1772732517.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata When APIC timer virtualization is enabled, the hardware handles the access to the guest TSC deadline MSR, not by the VMM. Disable/enable MSR intercept on TSC DEADLINE MSR based on the APIC timer virtualization bit of tertiary processor-based execution control. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/nested.c | 22 ++++++++++++++++++++++ arch/x86/kvm/vmx/nested.h | 5 +++++ 2 files changed, 27 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 1bd5e164e285..8bb8734cc690 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -598,6 +598,26 @@ static inline void enable_x2apic_msr_intercepts(unsign= ed long *msr_bitmap) } } =20 +static inline void prepare_tsc_deadline_msr_intercepts(struct vmcs12 *vmcs= 12, + unsigned long *msr_bitmap_l1, + unsigned long *msr_bitmap_l0) +{ + if (nested_cpu_has_guest_apic_timer(vmcs12)) { + if (vmx_test_msr_bitmap_read(msr_bitmap_l1, MSR_IA32_TSC_DEADLINE)) + vmx_set_msr_bitmap_read(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + else + vmx_clear_msr_bitmap_read(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + + if (vmx_test_msr_bitmap_write(msr_bitmap_l1, MSR_IA32_TSC_DEADLINE)) + vmx_set_msr_bitmap_write(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + else + vmx_clear_msr_bitmap_write(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + } else { + vmx_set_msr_bitmap_read(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + vmx_set_msr_bitmap_write(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + } +} + #define BUILD_NVMX_MSR_INTERCEPT_HELPER(rw) \ static inline \ void nested_vmx_set_msr_##rw##_intercept(struct vcpu_vmx *vmx, \ @@ -745,6 +765,8 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct= kvm_vcpu *vcpu, } } =20 + prepare_tsc_deadline_msr_intercepts(vmcs12, msr_bitmap_l1, msr_bitmap_l0); + /* * Always check vmcs01's bitmap to honor userspace MSR filters and any * other runtime changes to vmcs01's bitmap, e.g. dynamic pass-through. diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index 52bf035bcc03..6df2cfb20d87 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -286,6 +286,11 @@ static inline bool nested_cpu_has_encls_exit(struct vm= cs12 *vmcs12) return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING); } =20 +static inline bool nested_cpu_has_guest_apic_timer(struct vmcs12 *vmcs12) +{ + return nested_cpu_has3(vmcs12, TERTIARY_EXEC_GUEST_APIC_TIMER); +} + /* * if fixed0[i] =3D=3D 1: val[i] must be 1 * if fixed1[i] =3D=3D 0: val[i] must be 0 --=20 2.45.2