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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 17:17:16.5693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c18dade4-af13-4e33-3c5a-08ddbfd59ea4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6070 Content-Type: text/plain; charset="utf-8" When the io_alloc feature is enabled, a portion of the cache can be configured for shared use between hardware and software. Update the bit_usage representation to reflect the io_alloc configuration. Signed-off-by: Babu Moger --- v7: New patch split from earlier patch #5. Added resctrl_io_alloc_closid() to return max COSID. --- Documentation/filesystems/resctrl.rst | 20 ++++++++++----- fs/resctrl/rdtgroup.c | 37 +++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 8 deletions(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index c7949dd44f2f..c3c412733632 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -89,12 +89,20 @@ related to allocation: must be set when writing a mask. =20 "shareable_bits": - Bitmask of shareable resource with other executing - entities (e.g. I/O). User can use this when - setting up exclusive cache partitions. Note that - some platforms support devices that have their - own settings for cache use which can over-ride - these bits. + Bitmask of shareable resource with other executing entities + (e.g. I/O). Applies to all instances of this resource. User + can use this when setting up exclusive cache partitions. + Note that some platforms support devices that have their + own settings for cache use which can over-ride these bits. + + When "io_alloc" feature is enabled, a portion of the cache + can be configured for shared use between hardware and software. + + "bit_usage" should be used to see which portions of each cache + instance is configured for hardware use via "io_alloc" feature + because every cache instance can have its "io_alloc" bitmask + configured independently. + "bit_usage": Annotated capacity bitmasks showing how all instances of the resource are used. The legend is: diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 77d08229d855..a2eea85aecc8 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1030,6 +1030,20 @@ static int rdt_shareable_bits_show(struct kernfs_ope= n_file *of, return 0; } =20 +/* + * resctrl_io_alloc_closid() - io_alloc feature routes I/O traffic using + * the highest available CLOSID. Retrieve the maximum CLOSID supported by = the + * resource. Note that if Code Data Prioritization (CDP) is enabled, the n= umber + * of available CLOSIDs is reduced by half. + */ +static u32 resctrl_io_alloc_closid(struct rdt_resource *r) +{ + if (resctrl_arch_get_cdp_enabled(r->rid)) + return resctrl_arch_get_num_closid(r) / 2 - 1; + else + return resctrl_arch_get_num_closid(r) - 1; +} + /* * rdt_bit_usage_show - Display current usage of resources * @@ -1063,15 +1077,17 @@ static int rdt_bit_usage_show(struct kernfs_open_fi= le *of, =20 cpus_read_lock(); mutex_lock(&rdtgroup_mutex); - hw_shareable =3D r->cache.shareable_bits; list_for_each_entry(dom, &r->ctrl_domains, hdr.list) { if (sep) seq_putc(seq, ';'); + hw_shareable =3D r->cache.shareable_bits; sw_shareable =3D 0; exclusive =3D 0; seq_printf(seq, "%d=3D", dom->hdr.id); for (i =3D 0; i < closids_supported(); i++) { - if (!closid_allocated(i)) + if (!closid_allocated(i) || + (resctrl_arch_get_io_alloc_enabled(r) && + i =3D=3D resctrl_io_alloc_closid(r))) continue; ctrl_val =3D resctrl_arch_get_config(r, dom, i, s->conf_type); @@ -1099,6 +1115,23 @@ static int rdt_bit_usage_show(struct kernfs_open_fil= e *of, break; } } + + /* + * When the "io_alloc" feature is enabled, a portion of the + * cache is configured for shared use between hardware and software. + */ + if (resctrl_arch_get_io_alloc_enabled(r)) { + if (resctrl_arch_get_cdp_enabled(r->rid)) + ctrl_val =3D resctrl_arch_get_config(r, dom, + resctrl_io_alloc_closid(r), + CDP_CODE); + else + ctrl_val =3D resctrl_arch_get_config(r, dom, + resctrl_io_alloc_closid(r), + CDP_NONE); + hw_shareable |=3D ctrl_val; + } + for (i =3D r->cache.cbm_len - 1; i >=3D 0; i--) { pseudo_locked =3D dom->plr ? dom->plr->cbm : 0; hwb =3D test_bit(i, &hw_shareable); --=20 2.34.1