From nobody Thu Apr 2 06:28:48 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 918263E5ECA; Thu, 5 Mar 2026 17:44:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732677; cv=none; b=LC6d5PyaPS/+gF+Xcx+AyWS0UIjrEYdbRnPWhixp18aRCuu2Rc9kuSEYa0+or6fzFD8LumvYpGYKEHiz1iW+jQIlzwlU7O2rZBJ0funviL7/n9ziI+MkDPiwA/ykqL2Cl+40GewMBytaEbA+iHDlWTW0L7vfxmhQu7RLogg9No0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772732677; c=relaxed/simple; bh=08yovv4kHpvB18sUdnUiqahcaPf2xrtmKjUIG/qy/84=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b6XUQc0ni/SyB6LmJAaYgxCRDX6az0sjrH2s5Nw4MIvK+uLNCECjoEBfbzcig274uBKQK8/V8WzMBN1aRa9YC2XS4u5akmtUscZPFakEETJID1HGtyH7bO5t62eISSGk2Yk/ZjbEF1UJ/F79+9ZK4Cc9//OCjkV4ySQb7TVO+k8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SSWES8Ww; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SSWES8Ww" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772732676; x=1804268676; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=08yovv4kHpvB18sUdnUiqahcaPf2xrtmKjUIG/qy/84=; b=SSWES8Ww4Clo0LpVrJPeppuqfJ3npcjGJmthzO2k6CkMCnenLl20OUCm h66wvXNWgngkeVhPRlxCaIW7X2eOnJBQUnckQ8wIA2pbGJWhNO1Uw82yG 72SNtya3soYFdK2F+l4U/SIkIlSernoqq+fdSiuK3+HFLHLho1oGDCLZp nfmNLyovH545wC8VHGaPd1uupEr10Z6/mbKjzCBMigMLs3IHej0G0r2fG 5fBFuyl8fGFyNP7Hpj+5sFHv3kfwNACnX/32MS1iWe/fbUE/T6/rQi3Rd qGwSPtL3rFndZy3rRx6KmsmOrfLJ5X/skHl7Ixw9osnRnLHZoKgg75jls A==; X-CSE-ConnectionGUID: Letf9nEZT5Cgw+fY5c/9Dw== X-CSE-MsgGUID: oWzqppd0QGqPP/UIfvgaWw== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="77431558" X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="77431558" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:35 -0800 X-CSE-ConnectionGUID: J7zvM55GTB2ZQKjv5n9KSQ== X-CSE-MsgGUID: 9Cgu3wgjTF2q9alRznE3iw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="223447857" Received: from mdroper-mobl2.amr.corp.intel.com (HELO localhost) ([10.124.220.244]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 09:44:34 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , Sean Christopherson , linux-kernel@vger.kernel.org, Yang Zhong Subject: [PATCH v2 06/36] KVM: VMX: Implement the hooks for VMX guest virtual deadline timer Date: Thu, 5 Mar 2026 09:43:46 -0800 Message-ID: <865b011e272dce6995119cbe41cdbd367bc2d8ad.1772732517.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yang Zhong Implement the hooks for the VMX backend for APIC timer virtualization to access the related VMCS fields. Signed-off-by: Yang Zhong Co-developed-by: Isaku Yamahata Signed-off-by: Isaku Yamahata --- Changes: v1 -> v2: Move kvm_cpu_apicv_active() before kvm_lapic_lvtt_timer_mode() as it checks in-kernel apic check. --- arch/x86/kvm/lapic.h | 5 ++ arch/x86/kvm/vmx/capabilities.h | 6 +++ arch/x86/kvm/vmx/main.c | 5 ++ arch/x86/kvm/vmx/vmx.c | 83 ++++++++++++++++++++++++++++++++- arch/x86/kvm/vmx/x86_ops.h | 5 ++ 5 files changed, 103 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 5e96299c31f7..2f510503f5b3 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -237,6 +237,11 @@ static inline int kvm_lapic_latched_init(struct kvm_vc= pu *vcpu) return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic-= >pending_events); } =20 +static inline int kvm_lapic_lvtt_timer_mode(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.apic->lapic_timer.timer_mode; +} + bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); =20 bool kvm_lapic_suppress_eoi_broadcast(struct kvm_lapic *apic); diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index 4e371c93ae16..c5cb098f579b 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -90,6 +90,12 @@ static inline bool cpu_has_vmx_preemption_timer(void) PIN_BASED_VMX_PREEMPTION_TIMER; } =20 +static inline bool cpu_has_vmx_apic_timer_virt(void) +{ + return vmcs_config.cpu_based_3rd_exec_ctrl & + TERTIARY_EXEC_GUEST_APIC_TIMER; +} + static inline bool cpu_has_vmx_posted_intr(void) { return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index dbebddf648be..ed20c859def3 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -994,6 +994,11 @@ struct kvm_x86_ops vt_x86_ops __initdata =3D { #ifdef CONFIG_X86_64 .set_hv_timer =3D vt_op(set_hv_timer), .cancel_hv_timer =3D vt_op(cancel_hv_timer), + .can_use_apic_virt_timer =3D vmx_can_use_apic_virt_timer, + .set_apic_virt_timer =3D vmx_set_apic_virt_timer, + .cancel_apic_virt_timer =3D vmx_cancel_apic_virt_timer, + .set_guest_tsc_deadline_virt =3D vmx_set_guest_tsc_deadline_virt, + .get_guest_tsc_deadline_virt =3D vmx_get_guest_tsc_deadline_virt, #endif =20 .setup_mce =3D vt_op(setup_mce), diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 4ccb2e42322d..b70641bfecab 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2802,7 +2802,8 @@ static int setup_vmcs_config(struct vmcs_config *vmcs= _conf, & ~TERTIARY_EXEC_GUEST_APIC_TIMER, MSR_IA32_VMX_PROCBASED_CTLS3); =20 - if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) + if (!IS_ENABLED(CONFIG_X86_64) || + !(_cpu_based_2nd_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) _cpu_based_3rd_exec_control &=3D ~TERTIARY_EXEC_GUEST_APIC_TIMER; =20 if (adjust_vmx_controls(KVM_REQUIRED_VMX_VM_EXIT_CONTROLS, @@ -8364,6 +8365,86 @@ void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) { to_vmx(vcpu)->hv_deadline_tsc =3D -1; } + +bool vmx_can_use_apic_virt_timer(struct kvm_vcpu *vcpu) +{ + if (vcpu->kvm->arch.vm_type !=3D KVM_X86_DEFAULT_VM) + return false; + + return cpu_has_vmx_apic_timer_virt() && + /* SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY and in-kernel apic */ + kvm_vcpu_apicv_active(vcpu) && + /* VMX guest virtual timer supports only TSC deadline mode. */ + kvm_lapic_lvtt_timer_mode(vcpu) =3D=3D APIC_LVT_TIMER_TSCDEADLINE && + /* KVM doesn't use RDTSC existing. Safeguard. */ + !(exec_controls_get(to_vmx(vcpu)) & CPU_BASED_RDTSC_EXITING); +} + +void vmx_set_apic_virt_timer(struct kvm_vcpu *vcpu, u16 vector) +{ + vmcs_write16(GUEST_APIC_TIMER_VECTOR, vector); + vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC_DEADLINE, MSR_TYPE_RW); + tertiary_exec_controls_setbit(to_vmx(vcpu), TERTIARY_EXEC_GUEST_APIC_TIME= R); +} + +void vmx_cancel_apic_virt_timer(struct kvm_vcpu *vcpu) +{ + vmx_enable_intercept_for_msr(vcpu, MSR_IA32_TSC_DEADLINE, MSR_TYPE_RW); + tertiary_exec_controls_clearbit(to_vmx(vcpu), TERTIARY_EXEC_GUEST_APIC_TI= MER); +} + +static u64 vmx_calc_deadline_l1_to_host(struct kvm_vcpu *vcpu, u64 l1_tsc) +{ + u64 host_tsc_now =3D rdtsc(); + u64 l1_tsc_now =3D kvm_read_l1_tsc(vcpu, host_tsc_now); + u64 host_tsc; + + /* 0 means that timer is disarmed. */ + if (!l1_tsc) + return 0; + + host_tsc =3D l1_tsc - vcpu->arch.l1_tsc_offset; + if (vcpu->arch.l1_tsc_scaling_ratio !=3D kvm_caps.default_tsc_scaling_rat= io) + if (u64_shl_div_u64(l1_tsc, + kvm_caps.tsc_scaling_ratio_frac_bits, + vcpu->arch.l1_tsc_scaling_ratio, + &host_tsc)) + host_tsc =3D ~0ull; + + /* + * Clamp the result on overflow. + * TSC deadline isn't supposed to overflow in practice. + * ~0ull is considered that the timer is armed, but won't fire in + * practical time frame. + */ + if (l1_tsc > l1_tsc_now && host_tsc <=3D host_tsc_now) + host_tsc =3D ~0ull; + /* + * Clamp the result on underflow. + * The past value means fire the timer immediately. + * Pick the obvious past value. + */ + if (l1_tsc <=3D l1_tsc_now && host_tsc > host_tsc_now) + host_tsc =3D 1ull; + + if (!host_tsc) + host_tsc =3D 1ull; + + return host_tsc; +} + +void vmx_set_guest_tsc_deadline_virt(struct kvm_vcpu *vcpu, + u64 guest_deadline_virt) +{ + vmcs_write64(GUEST_DEADLINE_VIR, guest_deadline_virt); + vmcs_write64(GUEST_DEADLINE_PHY, + vmx_calc_deadline_l1_to_host(vcpu, guest_deadline_virt)); +} + +u64 vmx_get_guest_tsc_deadline_virt(struct kvm_vcpu *vcpu) +{ + return vmcs_read64(GUEST_DEADLINE_VIR); +} #endif =20 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/x86_ops.h b/arch/x86/kvm/vmx/x86_ops.h index d09abeac2b56..364050e0427c 100644 --- a/arch/x86/kvm/vmx/x86_ops.h +++ b/arch/x86/kvm/vmx/x86_ops.h @@ -117,6 +117,11 @@ void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcp= u); int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, bool *expired); void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu); +bool vmx_can_use_apic_virt_timer(struct kvm_vcpu *vcpu); +void vmx_set_apic_virt_timer(struct kvm_vcpu *vcpu, u16 vector); +void vmx_cancel_apic_virt_timer(struct kvm_vcpu *vcpu); +void vmx_set_guest_tsc_deadline_virt(struct kvm_vcpu *vcpu, u64 guest_dead= line_tsc); +u64 vmx_get_guest_tsc_deadline_virt(struct kvm_vcpu *vcpu); #endif void vmx_setup_mce(struct kvm_vcpu *vcpu); =20 --=20 2.45.2