From nobody Mon Feb 9 03:34:17 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6BD11EF0B6; Thu, 30 Jan 2025 17:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258574; cv=none; b=CySHyPPn4gomg8y8OdwjRtmCsXdp0YzD2WMZ4f0HT8QfdzTNje02xlXwqtooUcogfg12cCGLejuiOSaeA+613DeSyiv20xl7CxGQfQShm7jbCKhOs6mlb9bd9a59V60F+8jOdEmClWpRUwMl9nkpZTrtmfVpIJAwDDX3/XaUkjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258574; c=relaxed/simple; bh=EWDYRLDJNCSj8RgMr4ncDCesuiq7qtH/1S45Wc/TEoI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hXTjvJnkfXkXzKOyLpc0XiOzGVqOd9KnrI0XDNgiroAASPyYTwANXK0oM+tFikH9TWw/f8ngveAoKtPk8VrB5C2RZAAIh1JFXdYkTxjYWcwsVJNTAkbO/g7cpUizCzAQBLuH3ZjIEUFJ6ekU+MvXpR5SQX8f7VsGBzeNnRBBXvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=DMSULMaL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="DMSULMaL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258572; x=1769794572; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EWDYRLDJNCSj8RgMr4ncDCesuiq7qtH/1S45Wc/TEoI=; b=DMSULMaLlJLVE5S40NpXK+0sZITsBpMxxekHFNMETBp0z7gKuMJKwy3X edyjDxMjV7KPeh7US/3V6vfFqRAQI/aAEnz/TJsqt+St3ONoG2cD0XQun LD83IbW4o3Jd8BNm20Evy9oA190a/3EBw+4uvq/OaOh1lhVA14ImVO30b Bb2MEHBI3b0doxFbRFnSzgiU7x4Y0ni2cm1b7I10W0wj+uaVl95TU39Hf fsS9ng1Q13LrbhB1vAYocDZPd9ojVTJH4yiB+dfZ85O+y+ykaChrwyBYE njQM1c/JR5sga8sEJrwwMWYkKsHsbNEfv8xr43k64II+XPWYk7objsS2X g==; X-CSE-ConnectionGUID: 7iQ0c/B2QHylE8DKLR4q+g== X-CSE-MsgGUID: R4Kkehl8R8mgFbR+LWh4IA== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="41090047" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:41 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:41 -0700 From: To: , , , , , , , , , CC: , , , , , Li Bin , Ryan Wanner , Durai Manickam KR , Andrei Simion Subject: [PATCH 10/16] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Date: Thu, 30 Jan 2025 10:33:50 -0700 Message-ID: <862773938ff0b1265cf1e7a5b11ae0eb5b03cb2f.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Li Bin For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error" during recalibrating the impedance in BootStrap. We found that the impedance value saved in at91_suspend_finish() before the DDR entered self-refresh mode did not match the resistor values. The ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to select the different impedance setting. But these gray code are incorrect, a workaournd from design team fixed the bug in the calibration logic. The ZDATA contains four independent impedance elements, but the algorithm combined the four elements into one. The elemen= ts were fixed using properly shifted offsets. Signed-off-by: Li Bin [nicolas.ferre@microchip.com: fix indentation and combine 2 patches] Signed-off-by: Nicolas Ferre Tested-by: Ryan Wanner Tested-by: Durai Manickam KR Tested-by: Andrei Simion --- arch/arm/mach-at91/pm.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 05a1547642b60..32b8354738752 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz; =20 static int at91_suspend_finish(unsigned long val) { - unsigned char modified_gray_code[] =3D { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, - 0x10, 0x11, + /* SYNOPSYS workaround to fix a bug in the calibration logic (SYNOPSYS Ca= se Number 01331341) */ + unsigned char modified_fix_code[] =3D { + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18, + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13, + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14, + 0x1e, 0x1f, }; unsigned int tmp, index; int i; @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val) * restore the ZQ0SR0 with the value saved here. But the * calibration is buggy and restoring some values from ZQ0SR0 * is forbidden and risky thus we need to provide processed - * values for these (modified gray code values). + * values for these. */ tmp =3D readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); =20 /* Store pull-down output impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] =3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] =3D modified_fix_code[index] << DDR3PH= Y_ZQ0SR0_PDO_OFF; =20 /* Store pull-up output impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SR0_PUO_OFF; =20 /* Store pull-down on-die termination impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SR0_PDODT_OFF; =20 /* Store pull-up on-die termination impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SRO_PUODT_OFF; =20 /* * The 1st 8 words of memory might get corrupted in the process --=20 2.43.0