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Thu, 18 Dec 2025 13:43:25 -0800 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH rc v5 2/4] iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence Date: Thu, 18 Dec 2025 13:41:57 -0800 Message-ID: <83f991cbbb1331213aabe7c1fc5f725e79f60ecd.1766093909.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055E1:EE_|IA4PR12MB9785:EE_ X-MS-Office365-Filtering-Correlation-Id: 5aec7b5d-1e45-42b4-5846-08de3e7e83aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?D9IBsunJ8A4zlYCyZ0vodUIeHauOeZOQ5Jrf6Ygkiez25UDAbK3a02puJAGq?= =?us-ascii?Q?nj/MobZ3H51uVMN/maJbUPbQRLbw9ij3CyeEUQQIf04SFRu0VKb++0lUnNme?= =?us-ascii?Q?hMhaGd0/EYr9w+7zpN1O0xqP/GQ+RG4Qry4F5My5OYY0wzv8WorhywWHuMkC?= =?us-ascii?Q?OH3qnxpc3T2K1T+lhlANGHhywz6RViL7SNbz2JKogjFfcJxrU0TX5DAhkmR0?= =?us-ascii?Q?hNRo39QfqALBuJ6qvSCjW0TVM0kyeoluYuzNE24mg7sjJB2aKXsHh5RTds4p?= =?us-ascii?Q?Zflv5h29yYGW6H8yCx14GykmjUhYsFlvYgWeHOioqFs2eVaHTlWMnnv0W2ZK?= =?us-ascii?Q?vqoxxDa4a8o09P/H3y+byahtWB77sjTL/wwJuT+0PKLX1F98pqu1ptDrRWh2?= =?us-ascii?Q?Lbjmu1lfxATyoYHYwhgLeQGifKm1XuFTaYBfTckac2ZuON6JkkCMryvnvr2z?= =?us-ascii?Q?u7IchhBbYGedT4cqKOegmVMsVwgyo5wHCToSNeH4LKHAciWtKnPiTYCINLeW?= =?us-ascii?Q?qhF6DbSi9geAgBUGOhHAmF+SFq9isupgTLuhhezXd3KGBIvwNsC1pD47/GV5?= =?us-ascii?Q?2OzSY45bIAoPoIzSKUT7/Cxj4g5wMcFj6Pw3ZfeNJFVgQiUAp1PewYFvHCF9?= =?us-ascii?Q?uL+wgiCVipeuTi+0a2yCCtM15C0X8uc3oI45karGlqwSjyfg422FTDGPpu6l?= =?us-ascii?Q?ic8GMQMd8WsYSlY/7S5M3atyo4qM0z1rqg6TdCzSEwQEnjjs0e3Ij6mL8wHm?= =?us-ascii?Q?/LFiOccovP8zxKIwrGTAbF9DilnuElZxeQRnYYMkq6pdxekBCIVghld8wB6d?= =?us-ascii?Q?qFSMYZ1BftSaMCOx/3GTOK4bKj/pV8RBIFme/NwjZbinuknm1Hxy1feCcYUS?= =?us-ascii?Q?YuEmZvBIeWgiUrd6Yd1PtebHR5DA2F5NAzFNThnGPMpvlsTSm5ihmhzdbCtv?= =?us-ascii?Q?35ottXt6nWt+yeL79hxFz0+x9ev/j2owj3xuK/6IAe19r9kcQQI1QXppszcx?= =?us-ascii?Q?pd7QTkuBREL+bXhPW54aAgEzBinydf10TZahll3lwe8bC2kpv/2kpMHnfWR3?= =?us-ascii?Q?UQjqehXyYUKP+C12y8eivdxJ7KC+WOqSE8Pkfj8K+/jXMxdARSGLvNKfS5Wh?= =?us-ascii?Q?q5Pmn5saLvU/nkuHmzwfxjA9e0dGqCuOzJukeSHrJYJYGle4D9A0tmOsRHzB?= =?us-ascii?Q?8dSyLGDh3C2YyMAZMkOC8LNs+ylcGK52g/RLewhAYhoRvgwz/isuwl2prKst?= =?us-ascii?Q?nedPpt79kSyBes61vFVlaKDTnt4M0UzSh/U2XaBKC4Pn4qSuOwObvyeYuDro?= =?us-ascii?Q?g374x6OADr9KQkWisKmzzUwSR/Z4vCQpVBqSfrdpDn9THOSAt7wR7ZzAd1WW?= =?us-ascii?Q?R2Cv1+hhoh1T5NABYkkJa9Kpgu363KlmBOy8aLx4XveNAOnkzGvcJHh3wc5D?= =?us-ascii?Q?HE1dTuuEaajWgygSoy8A8rP3zrRw30bXO/UFu3gBvFm6G/Bivro3yADwqtNg?= =?us-ascii?Q?1cL2dsGQ9KadpOP51JPNjbSdE7a0oKVvYGArBFevwCcTNwMrVvfRwNfeMyhC?= =?us-ascii?Q?v4sVIn1t9SUmbgItlsM=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 21:43:42.7280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5aec7b5d-1e45-42b4-5846-08de3e7e83aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E1.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR12MB9785 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Nested CD tables set the MEV bit to try to reduce multi-fault spamming on the hypervisor. Since MEV is in STE word 1 this causes a breaking update sequence that is not required and impacts real workloads. For the purposes of STE updates the value of MEV doesn't matter, if it is set/cleared early or late it just results in a change to the fault reports that must be supported by the kernel anyhow. The spec says: Note: Software must expect, and be able to deal with, coalesced fault records even when MEV =3D=3D 0. So mark STE MEV safe when computing the update sequence, to avoid creating a breaking update. Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS = mitigations") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8dbf4ad5b51e..12a9669bcc83 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); VISIBLE_IF_KUNIT void arm_smmu_get_ste_update_safe(__le64 *safe_bits) { + /* + * MEV does not meaningfully impact the operation of the HW, it only + * changes how many fault events are generated, thus we can relax it + * when computing the ordering. The spec notes the device can act like + * MEV=3D1 anyhow: + * + * Note: Software must expect, and be able to deal with, coalesced + * fault records even when MEV =3D=3D 0. + */ + safe_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe); =20 --=20 2.43.0