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Tue, 16 Dec 2025 20:26:15 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH rc v4 2/4] iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence Date: Tue, 16 Dec 2025 20:26:00 -0800 Message-ID: <83f991cbbb1331213aabe7c1fc5f725e79f60ecd.1765945258.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|DS7PR12MB6358:EE_ X-MS-Office365-Filtering-Correlation-Id: f88b7b2f-a548-413f-41bc-08de3d24717b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8pZLNspOgx/QXBGZX+EkAQ14Pe+v3wV2oOqV5T+pyw/l0M7jJTBoVbrZnW6M?= =?us-ascii?Q?ZmWvx5ysCdxm6tXHtGB6M2qXyUjxIJWXq5C0PmQpmFbJBFcwrvoV3syF0siP?= =?us-ascii?Q?maXbOpI73L5G0JI++YW8j7wTjoc2DcStsnkrtvP5phOYRFayggWXgHY1isoa?= =?us-ascii?Q?rJ3QsZCXfbTH8iGUm4jhO5fWRsVuhSdPBrxqgoVskkY1C7zr3Pg9EUPVTYPq?= =?us-ascii?Q?R4B3Pe3gsV4PcXV++BQ71GKCl7ZWldr0GVjmEbsKEqLo+hrAxTGeuwWXM35p?= =?us-ascii?Q?DYdDkJky67cMdTonTlO0C1ocqttduvfGhE41HK+cQnvm92f77p1sORdYIB8v?= =?us-ascii?Q?oX7bU4Y+3B73cAQZkcI0CisB1jNIJ0B0Any4e4zVVzu79fYjfN987f5iTGQR?= =?us-ascii?Q?wPFgEQ+QhKJJKmt87LYTh4d5KsRvIBUjlHB1GBhhWIk5t8slVGPaeGyWLG30?= =?us-ascii?Q?dTmq1lVNSZgSlN/Y7pYDHXljZqQvjTbD4qhYmzUb/BuJAphDiGshOrzf15Bo?= =?us-ascii?Q?/IR5iZnf9rkPug6FuQrUvmD8gFH3JZfX+tRbIFWhUmE+dWFASVYIznTttndI?= =?us-ascii?Q?2eBAPEJnKMQ6Q1mxjzcLLdOz+/DfpIxtT88MxLaMt/DgI1hvX3s5gS1jcPmC?= =?us-ascii?Q?E30OWp3Hi72Ka68DK3keLcKu8iKBNWgdbG2tl50SaRjP6KMh0TsXHNlcxZc2?= =?us-ascii?Q?qkyg4vLRA04IlvDzzKi5I91K/TVN8z/BC4azTu+ra8jB5nIndL21748jyylq?= =?us-ascii?Q?QQTI9ZgBvG5noejJ1MnmTvfmNG3KGvqBtVjDFjpxEPkqfp1m95XOYK/DqlcH?= =?us-ascii?Q?AWgA27eJPuEal4yRZ5Tuyha4VHlPZclyoKZeDP309MYsoY/wpY+LUV6/NJf0?= =?us-ascii?Q?B6/1yyKgcaJ8Ibrnta59rUEtrDY7+5Mt+cFS/ImkbNZWtKOIHp6uXHERSagn?= =?us-ascii?Q?PWydhq54as4iP3mL9lm431WeEYmwtKWEOfR9LVLN37i4SCOAR+ywgZuW8Ifp?= =?us-ascii?Q?3VirRG9C+jarqJSsYSvVU8qrKnk1oNNc6riPRZUnkiDvSvNKyGQeWVbeSths?= =?us-ascii?Q?EIJk0JiAYRLxFcDGGGEknsV/21y5IZOKYE0FWxqLUTQhUbeYaWXYm83H+32M?= =?us-ascii?Q?3YrBBaPYWNVQQJ4Hbw0XqqkmTKrttFdW5aqkbOPEl0XQjBc1t/7C07D2Qb3w?= =?us-ascii?Q?I00bcTddQGRpq9ynYcWdCDmRgwGrILPim6E5KDioSweKklZtfR3jDqz9k+i0?= =?us-ascii?Q?tz8pkIpJJfJaSBkz71zRANnr6LPW91x65mREdMnYpWxF/AN9ysRvtYHJmbTh?= =?us-ascii?Q?l+TXUkYpl1w42Rf/AmiZZOrbtNYNOPXOYFwGrSUX/iMLjNHYcuX0goH2Vt9U?= =?us-ascii?Q?qIYrjQQl9GF0q5Vda8nPnxYD469oX79TooG0jMlpdGqLwDKrcbZl8M1+RfE2?= =?us-ascii?Q?DMFnP7njCazHregcWP5uEfyt9nRcnaxFoZPlAPIhB5xedG6rn6quPGilpwVT?= =?us-ascii?Q?J1NmOqzMmmKO7QLiD7UA8kG+Fu8UBUrdzW1FxTKpLlcj0XI7G1JSJ5Hhqj3L?= =?us-ascii?Q?EVZpJ94cH5O1u6rWIo4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2025 04:26:26.3605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f88b7b2f-a548-413f-41bc-08de3d24717b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6358 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Nested CD tables set the MEV bit to try to reduce multi-fault spamming on the hypervisor. Since MEV is in STE word 1 this causes a breaking update sequence that is not required and impacts real workloads. For the purposes of STE updates the value of MEV doesn't matter, if it is set/cleared early or late it just results in a change to the fault reports that must be supported by the kernel anyhow. The spec says: Note: Software must expect, and be able to deal with, coalesced fault records even when MEV =3D=3D 0. So mark STE MEV safe when computing the update sequence, to avoid creating a breaking update. Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS = mitigations") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8dbf4ad5b51e..12a9669bcc83 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); VISIBLE_IF_KUNIT void arm_smmu_get_ste_update_safe(__le64 *safe_bits) { + /* + * MEV does not meaningfully impact the operation of the HW, it only + * changes how many fault events are generated, thus we can relax it + * when computing the ordering. The spec notes the device can act like + * MEV=3D1 anyhow: + * + * Note: Software must expect, and be able to deal with, coalesced + * fault records even when MEV =3D=3D 0. + */ + safe_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe); =20 --=20 2.43.0