From nobody Sat Oct 4 01:41:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E42EF2C21C3; Thu, 21 Aug 2025 18:22:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800580; cv=none; b=KU5YAT1P+kiO1uUYdwMXeMnFyFxEmMvohd1ptSaSuXlkB2cQtxuf9R1vjTHKXDVMCiRZN4bllCw3cbKs/9Rah066U/NtKONtYPUYJcYgSrcNCwsINVv9Y0s7UVBhdSo0jeBEpMDnMp3o6joxEefYBklzuFiQr6t1oiG8qR21oNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800580; c=relaxed/simple; bh=trQVciou02BhqLI+wLFz+BJzOyksrkiGATsW4fd67aE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fZ3+6pLxnUqxRrkFNgjg3VEeLEbhWY5dpoEnIAcTlicnuomei0/cS72Fdzmd9AkvQG3goySa+LrOB8PoZKWIT0L/rlQxFMZEVsUbBaJsRBfHlkVVIsPUpqibdsgVwnQsXSunNDsp+C6obnM7nwyZW2MJ4z+SAjk5cjqrByhpIH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b7s/L6+5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b7s/L6+5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF416C4CEEB; Thu, 21 Aug 2025 18:22:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800579; bh=trQVciou02BhqLI+wLFz+BJzOyksrkiGATsW4fd67aE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b7s/L6+5Fk8KOSKcdHN/llciet0ETx9ev0EY5VxZjKkU2gKZvpTpqdjCak78wc5Vw A3MhfqzgLDDTO+3XfRYBrvsKOS/K633fygH0NGlZC3HlpA6jGGCbm6lf+ZH+KBiGGv tSVunXP5T1ckJW1ENJ9BwKOiWDNjpXivyRn+PuTqGKO+Ca+8Gox+cjZcPTcR5IdRG/ Kqi8upLo7MdXDQGD8Gum1BeOeozvCH8iwvJvT4ZhUw3KYX79qnyGCIpyI00a2qzFb7 D6ggmXtl7pot7tv691m2yubkLvrjIZM//oVR4SNGbMR6JKuuS9dBOXHwxFBfDiDhrI TqiZAZQ6UMKrg== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 2/7] KVM: SVM: Add a helper to look up the max physical ID for AVIC Date: Thu, 21 Aug 2025 23:48:33 +0530 Message-ID: <82992eac8f3a2424373001d76526f418276532a5.1755797611.git.naveen@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To help with a future change, add a helper to look up the maximum physical ID depending on the vCPU AVIC mode. No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a6908ac5298d..4f00e31347c3 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -79,13 +79,31 @@ static bool next_vm_id_wrapped =3D 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); bool x2avic_enabled; =20 +static u32 avic_get_max_physical_id(struct kvm_vcpu *vcpu) +{ + u32 arch_max; + + if (x2avic_enabled && apic_x2apic_mode(vcpu->arch.apic)) + arch_max =3D X2AVIC_MAX_PHYSICAL_ID; + else + arch_max =3D AVIC_MAX_PHYSICAL_ID; + + /* + * Despite its name, KVM_CAP_MAX_VCPU_ID represents the maximum APIC ID p= lus one, + * so the max possible APIC ID is one less than that. + */ + return min(vcpu->kvm->arch.max_vcpu_ids - 1, arch_max); +} + static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb =3D svm->vmcb01.ptr; - struct kvm *kvm =3D svm->vcpu.kvm; + struct kvm_vcpu *vcpu =3D &svm->vcpu; =20 vmcb->control.int_ctl &=3D ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); + vmcb->control.avic_physical_id &=3D ~AVIC_PHYSICAL_MAX_INDEX_MASK; + vmcb->control.avic_physical_id |=3D avic_get_max_physical_id(vcpu); =20 vmcb->control.int_ctl |=3D AVIC_ENABLE_MASK; =20 @@ -98,8 +116,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |=3D X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, - X2AVIC_MAX_PHYSICAL_ID); + /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -109,9 +126,6 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu); =20 - /* For xAVIC and hybrid-xAVIC modes */ - vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, - AVIC_MAX_PHYSICAL_ID); /* Enabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, true); } --=20 2.50.1