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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT062.mail.protection.outlook.com (10.13.177.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6588.34 via Frontend Transport; Wed, 19 Jul 2023 06:57:27 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Jul 2023 01:57:07 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 3/6] x86/cpuid: Add smp helper Date: Wed, 19 Jul 2023 12:25:38 +0530 Message-ID: <827723d8f506411700c68bccc5072ec8d918d2de.1689748843.git.sandipan.das@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT062:EE_|PH7PR12MB8153:EE_ X-MS-Office365-Filtering-Correlation-Id: dfdd8ef2-c606-4d12-499a-08db88256a18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 06:57:27.7732 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfdd8ef2-c606-4d12-499a-08db88256a18 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8153 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Depending on which CPU the CPUID instruction is executed, some leaves can report different values. There are cases where it may be required to know all possible values. E.g. for AMD Zen 4 processors, the ActiveUmcMask field from leaf 0x80000022 ECX, which provides a way to determine the active memory controllers, can have different masks on CPUs belonging to different sockets as each socket can follow a different DIMM population scheme. Each memory channel is assigned a memory controller (UMC) and if no DIMMs are attached to a channel, the corresponding memory controller is inactive. There are performance monitoring counters exclusive to each memory controller which need to be represented under separate PMUs. So, it will be necessary to know the active memory controllers on each socket during the initialization of the UMC PMUs irrespective of where the uncore driver's module init runs. Add a new helper that executes CPUID on a particular CPU and returns the EAX, EBX, ECX and EDX values. Signed-off-by: Sandipan Das --- arch/x86/include/asm/cpuid.h | 14 ++++++++++++++ arch/x86/lib/Makefile | 2 +- arch/x86/lib/cpuid-smp.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 arch/x86/lib/cpuid-smp.c diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h index 9bee3e7bf973..17e74d4584f5 100644 --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -150,6 +150,20 @@ static __always_inline bool cpuid_function_is_indexed(= u32 function) return false; } =20 +#ifdef CONFIG_SMP +int cpuid_on_cpu(unsigned int cpu, unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx); +#else /* CONFIG_SMP */ +static inline int cpuid_on_cpu(unsigned int cpu, unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + cpuid(op, eax, ebx, ecx, edx); + return 0; +} +#endif /* CONFIG_SMP */ + #define for_each_possible_hypervisor_cpuid_base(function) \ for (function =3D 0x40000000; function < 0x40010000; function +=3D 0x100) =20 diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index ea3a28e7b613..e0097ae55edf 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -39,7 +39,7 @@ $(obj)/inat.o: $(obj)/inat-tables.c =20 clean-files :=3D inat-tables.c =20 -obj-$(CONFIG_SMP) +=3D msr-smp.o cache-smp.o +obj-$(CONFIG_SMP) +=3D msr-smp.o cache-smp.o cpuid-smp.o =20 lib-y :=3D delay.o misc.o cmdline.o cpu.o lib-y +=3D usercopy_$(BITS).o usercopy.o getuser.o putuser.o diff --git a/arch/x86/lib/cpuid-smp.c b/arch/x86/lib/cpuid-smp.c new file mode 100644 index 000000000000..87340893ff61 --- /dev/null +++ b/arch/x86/lib/cpuid-smp.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include + +struct cpuid_info { + u32 op; + struct cpuid_regs regs; +}; + +static void __cpuid_smp(void *info) +{ + struct cpuid_info *rv =3D info; + + cpuid(rv->op, &rv->regs.eax, &rv->regs.ebx, &rv->regs.ecx, &rv->regs.edx); +} + +int cpuid_on_cpu(unsigned int cpu, unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + struct cpuid_info rv; + int err; + + memset(&rv, 0, sizeof(rv)); + + rv.op =3D op; + err =3D smp_call_function_single(cpu, __cpuid_smp, &rv, 1); + *eax =3D rv.regs.eax; + *ebx =3D rv.regs.ebx; + *ecx =3D rv.regs.ecx; + *edx =3D rv.regs.edx; + + return err; +} +EXPORT_SYMBOL(cpuid_on_cpu); --=20 2.34.1