From nobody Thu Apr 2 01:50:51 2026 Received: from mail-43103.protonmail.ch (mail-43103.protonmail.ch [185.70.43.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 010F52F260C for ; Mon, 30 Mar 2026 14:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.103 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774881262; cv=none; b=jd1cGNUitUcvKGI4P5gkpMtfB8OFUxNEUXlltZHB+Q3oahkPhVh6r7LdMLfoLlfZnIah8kzqeU7Sjq/ATlhdEwpWu1NwfOxf+4zD7oh9IwcpldgSiFReKf3k/me33sQ6O62/X03z52gNz40FQ0WmcDWW7rcP4S699x2ShbA/yUw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774881262; c=relaxed/simple; bh=Ha7lN9bSbT4rjqr83U4Yc2Wkef1ryrDJBI/LG3Mj2oQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cUk6YgZKEe0bJl3nMrvq8+3TIqHA94kmwW6sSILJpIobMIqQSBt5ktaKsx/xNkfEq9/mtBi4jZ29KbIpOc258FO6Nt46pbVKe6+Bkz8BR9/dA0+ifN5DDO33zH3k0GjPLTOunledvk3HCGpD3StLqA0/LqtG97mPxDcXXDFxdTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=INgmc5MI; arc=none smtp.client-ip=185.70.43.103 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="INgmc5MI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1774881258; x=1775140458; bh=8q+A+Haremrmiz+feKlaHxC2ccHzsYvDqSm9RyNCONM=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=INgmc5MI9zB1qGGlxqncRh7B6x8iAPDeRUTMBtVs1WxesFCNDLJKgrUq2ivxuqr// QiO31YFpIsi0L3cqzB7cIOY2DghVhlp5Dkz1WNcZURSY++1tLNphd9h6EHWjYyIHcF 2jZxmwGQor0nDtEdEHbbNEXy/WOtEGgVZvTFm9D08h7q1BQOGhlzai19HuJ0pHhT10 FV3o667VsAr9K/n0mz82y08lbvN10OIyuDlVxRJ1wl3+ERfhKuiOfhAsjBwcKLuGQd zfbcPc/yBpDOTfY8B5oleG9uH9JxecUAqvEjxfc9iqx8t5hOfFK26hBPlvmecBPh+o kRLj+yYRVbKbg== Date: Mon, 30 Mar 2026 14:34:13 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , Alexander Potapenko , linux-kernel@vger.kernel.org Subject: [PATCH v12 11/15] x86/mm: Initialize LAM_SUP Message-ID: <820f42da171d9a602d1c4cd83eefc7974025c642.1774872838.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 5f6782749c287a14d7ab8a7b4ee353d6e5040e7f Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman To make use of KASAN's tag based mode on x86, Linear Address Masking (LAM) needs to be enabled. To do a bit in CR4 has to be set. When launching secondary CPUs the LAM CR4 bit needs to be added to a mask in head_64.S. Bits that are not part of that mask are cleared when secondary CPUs are getting enabled by the primary one. Signed-off-by: Maciej Wieczor-Retman Acked-by: Alexander Potapenko --- Changelog v11: - Redo the patch message according to Dave's suggestions. Changelog v9: - Rename patch title so it fits the tip standards. Changelog v7: - Add Alexander's acked-by tag. Changelog v6: - boot_cpu_has() -> cpu_feature_enabled() arch/x86/kernel/head_64.S | 3 +++ arch/x86/mm/init.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 7ed5520dd52e..87d1c08fd932 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -209,6 +209,9 @@ SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL) * there will be no global TLB entries after the execution." */ movl $(X86_CR4_PAE | X86_CR4_LA57), %edx +#ifdef CONFIG_ADDRESS_MASKING + orl $X86_CR4_LAM_SUP, %edx +#endif #ifdef CONFIG_X86_MCE /* * Preserve CR4.MCE if the kernel will enable #MC support. diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index fb67217fddcd..11804ccf2fbb 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -763,6 +763,9 @@ void __init init_mem_mapping(void) probe_page_size_mask(); setup_pcid(); =20 + if (cpu_feature_enabled(X86_FEATURE_LAM) && IS_ENABLED(CONFIG_KASAN_SW_TA= GS)) + cr4_set_bits_and_update_boot(X86_CR4_LAM_SUP); + #ifdef CONFIG_X86_64 end =3D max_pfn << PAGE_SHIFT; #else --=20 2.53.0