From nobody Mon Apr 6 23:11:14 2026 Received: from mail-43101.protonmail.ch (mail-43101.protonmail.ch [185.70.43.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C62A14594A for ; Tue, 17 Mar 2026 20:00:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773777629; cv=none; b=XsjWnL0GZ9dYw64Ob/hlGG5RaqhrJiyETajdsHVSAWlWEt7HMeijhV66SJ0HlGvTKx0MkxK8NSZduPiP6ir5PT4fFGhkIsRFRzDNHKrznY1hm+nDGgOi8uhuvZvfXjPI6CiG4MUmWS76Op+/ZUxr+NyXhNIYECg9Ahz6qEJW9Pw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773777629; c=relaxed/simple; bh=DLJ/wBanpCBGgXiAykEdxvWB6InIx0nVkdPWTMarDsU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g3qHwRseArsk7tUIL/tNsIq1zbvIs8hvbRdwxDyEesMm5bX8uzlbNs1Z2wEqBpuN9btVIya6KMkFap7CmMtN3jv0cFT3E9LwmcLxnzmFnjJPOA1WPC68iLwm1D0LEW3RwcRVCCg5SDn8oArYXL03ZlIjvkkytrDtnxRpOOjHUIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=eLIeBBbO; arc=none smtp.client-ip=185.70.43.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="eLIeBBbO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1773777625; x=1774036825; bh=9euF1L4BnGlm1DIdBR//NKl0H9spKn39cectNzroKqY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=eLIeBBbOwJbeUhpR1Gel4K2LTuMU8mo19SBbgUtdzNTHzOlE0JX/9GIMvXr9pHmuQ dKYq0ITM+5JFZ2V/6pdVdDvQ7RQpunNo4x80sxYSnNumXiINS+Rk+QkSIGsUNuti54 NHRPHxkBDd3uPwSI7lWDF+PuCEkFoHIQFiFbDIGVtrdMVvjLELAKsGyodfCampj+jL rnck0LvSFMu59ZrEJc/ZoW5skI+FXmKjXDvdzj3xE5ayWTvkV9uosRtVba+USzvKa8 1o3GBLO1U4ISn8krdoOarPJ2lOAcxwSP8PAFF91HdoUDs+e1i9B3OlTYRBdIBdIArA 91S5ljBykdPPw== Date: Tue, 17 Mar 2026 20:00:22 +0000 To: tglx@kernel.org, bp@alien8.de, mingo@redhat.com, darwi@linutronix.de, thuth@redhat.com, dave.hansen@linux.intel.com, ak@linux.intel.com, babu.moger@amd.com, chang.seok.bae@intel.com, peterz@infradead.org, nik.borisov@suse.com, jpoimboe@kernel.org, pawan.kumar.gupta@linux.intel.com, hpa@zytor.com, xin@zytor.com, maciej.wieczor-retman@intel.com, sohil.mehta@intel.com From: Maciej Wieczor-Retman Cc: x86@kernel.org, linux-kernel@vger.kernel.org, m.wieczorretman@pm.me Subject: [PATCH v10 3/3] x86/cpu: Do a sanity check on required feature bits Message-ID: <8180d2f5c3da2737167418d3a28b008a933c6408.1773771353.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: e43f64c2f475846df49dd39dbea0750c87061eae Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman After CPU identification concludes, do a sanity check by comparing the final x86_capability bitmask with the pre-defined required feature bits. Signed-off-by: Maciej Wieczor-Retman Acked-by: H. Peter Anvin (Intel) Reviewed-by: Pawan Gupta Reviewed-by: Sohil Mehta --- Changelog v10: - Shorten the comment before the sanity check. - cpu -> CPU in the warning. - NCAPINTS << 5 -> NCAPINTS * 32 Changelog v9: - REQUIRED_MASK_INITIALIZER -> REQUIRED_MASK_INIT - Redo the comments. - Fix reverse xmas order. - Inside for_each_set_bit: (void *) -> (unsigned long *). - 16 -> X86_CAP_BUF_SIZE. Changelog v6: - Add Peter's acked-by tag. - Rename patch subject to imperative form. - Add a char buffer to the x86_cap_name() call. arch/x86/kernel/cpu/common.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0e318f3d56cb..badf86a26e24 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2005,6 +2005,33 @@ const char *x86_cap_name(unsigned int bit, char *buf) return buf; } =20 +/* + * As a sanity check compare the final x86_capability bitmask with the ini= tial + * predefined required feature bits. + */ +static void verify_required_features(const struct cpuinfo_x86 *c) +{ + u32 missing[NCAPINTS] =3D REQUIRED_MASK_INIT; + char cap_buf[X86_CAP_BUF_SIZE]; + unsigned int i; + u32 error =3D 0; + + for (i =3D 0; i < NCAPINTS; i++) { + missing[i] &=3D ~c->x86_capability[i]; + error |=3D missing[i]; + } + + if (!error) + return; + + /* At least one required feature is missing */ + pr_warn("CPU %d: missing required feature(s):", c->cpu_index); + for_each_set_bit(i, (unsigned long *)missing, NCAPINTS * 32) + pr_cont(" %s", x86_cap_name(i, cap_buf)); + pr_cont("\n"); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); +} + /* * This does the hard work of actually picking apart the CPU stuff... */ @@ -2134,6 +2161,8 @@ static void identify_cpu(struct cpuinfo_x86 *c) mcheck_cpu_init(c); =20 numa_add_cpu(smp_processor_id()); + + verify_required_features(c); } =20 /* --=20 2.53.0