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Wed, 22 Oct 2025 19:22:08 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 1/6] iommu: Generic support for RMRs during device release Date: Wed, 22 Oct 2025 19:21:04 -0700 Message-ID: <80bbe9125d90b001f3ce08429704aa4168b0a00b.1761017765.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|SN7PR12MB8771:EE_ X-MS-Office365-Filtering-Correlation-Id: 108e0cb7-760e-4063-ccda-08de11db0057 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?x/UNMLeWA17a8ENKszWEqUWPMbALU0Q/+iklg2FUhBee44SobM8wldo9Mt71?= =?us-ascii?Q?8OvQKD9T8jqxqG9itNxq+9cr7ayD/9xXRWTuo1Wn49DMuKqlUwKfKLgcGwoF?= =?us-ascii?Q?RNH3Tohk7MREseMDnFchkSZTrF5zW5deCOyb3KfZps6S/EQ3TyZu++IO2iJC?= =?us-ascii?Q?iQ78vAlAAM5BKsZwF1DTkdDumHz6FO3I2VS1Ga/Czbi+akl/X7lRLdijDm7g?= =?us-ascii?Q?+f5p9hHt2NbJotH2DEBKS0hCy/DM5oRjiJ6qY/g8bcmuYbkGXEW41W3jxlIL?= =?us-ascii?Q?dJDN72Nsyejtl9t3ctz/vuYucm7HOrdfvMuW8tZpFvSFICpienHHjfewiOIe?= =?us-ascii?Q?s7nNKm2dvwYkmjWLQb1HfjuQEu9UUxn9tPSE1HjOvFbtuuVnr6F3xry9irJM?= =?us-ascii?Q?WSt/ZNeHcJIB9nD84uv0mEhNtF+MGcyJDSVoYu3Q5DxsuFj5dnd28cQYDX9A?= =?us-ascii?Q?IcHxoyE9yetyKLJs/W9fBvsvSowhajuOmIy9CdcF04pOpo2m1401AktbbeA/?= =?us-ascii?Q?Rt6WXIltPxP4i98IAzinE1c3i32BrZrLqf7KFYxMKd0ZW47kqBuRNYTCgUHG?= =?us-ascii?Q?Yt9h/f1JmejBbtqOi7Xu3/w23bTm7JSq/mEB/QRJmnfuhI1KPKPrvJuijAcz?= =?us-ascii?Q?UsavqnMDZrYgZDk5yr54PMQeyZomJcr9gAMnYqSgSe4TWvtJz5vBvFAKbDck?= =?us-ascii?Q?y+dMc6Ur/KSqDTqQiyHAeI5jk3YVIGPxAsFimdvpgBTdu6sAipz0j8XA1S9c?= =?us-ascii?Q?l/4dcyWAFOkM21IJcbTr30KJ8X9rdswElKiUDoeyRfJvyvgReYSiF3nVuycX?= =?us-ascii?Q?3/a/W/kmjl/5SgBWTZsJ0TEfzDrtzMzsrrcbzBmSnmtKUhm+2FkwOzL0b59z?= =?us-ascii?Q?7aegehLK4vbdvs7PWWtqY/28Le2MwCSqkCPcNDj7631SmAUW9lGPkW1gPDkh?= =?us-ascii?Q?yKiFI+gRexvT4nIkzEzzaEp3ZVVf9o6ag3CjYmCv9s2o0ol10hrU101JonBp?= =?us-ascii?Q?UMKGCDmD/s4JkYAXj9Yzi+/gRtnrfSCgqeZZza4kWgoHcbEmUokPjGn0lg7H?= =?us-ascii?Q?WK5QhbmHkA86+8o1xWe83HhDnE/5g6fsBa3HIpDyDjd+8guN+M3Z/BxJuzRR?= =?us-ascii?Q?Fv2g5+iqUzkjPuSwMvXV/ZL5FNwWVnuoGPB/dGXeQyWFmixFktyT8PWHgmO9?= =?us-ascii?Q?gP+zmKYJ0Sov9SW4/AXs+UcxvSRsnMSldqUguVtBq16i6iRq8q3/C4lCg3hF?= =?us-ascii?Q?eeGqWk0Z2WsHViRhBsn2wK8kinHEhxXi+W98Ym5LjEqm9IRTRpunw3EtZ2Xc?= =?us-ascii?Q?Hq+H4MrtxjZ3aNvLSoOzFacGu6cHAL/GZF6ICIn+NHwwuteimF3KauddMUQ9?= =?us-ascii?Q?12ClZn1pHXdZM23mjmJhbjZlJyNRSOwi8U0IIMSAoB4+v4HNNNp9LhLVNJRc?= =?us-ascii?Q?XLkqTKR/7SAd7q2ZNzR+O3NmvaJDZiS+hLhERcn+1l5Lp+JMs/YrUSrwxpfQ?= =?us-ascii?Q?pBvXna4Rxvisrlr8Ea5U5s2wZKin1E+DQHjAlDuag5aNU1/Llg2ZT9KO/6tY?= =?us-ascii?Q?a+GHGIzN//vW2M3rSK8=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2025 02:22:23.3321 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 108e0cb7-760e-4063-ccda-08de11db0057 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8771 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Generally an IOMMU driver should leave the translation as BLOCKED until the translation entry is probed onto a struct device. When the struct device is removed, the translation should be put back to BLOCKED. Drivers that are able to work like this can set their release_domain to the blocking domain, and the core code handles this work. The exception is when the device has an IOMMU_RESV_DIRECT region, in which case the OS should continuously allow translations for the given range. And the core code generally prevents using a BLOCKED domain with this device. Continue this logic for the device release and hoist some open coding from drivers. If the device has dev->iommu->require_direct and the driver uses a BLOCKED release_domain, override it to IDENTITY to preserve the semantics. The only remaining required driver code for IOMMU_RESV_DIRECT should preset an IDENTITY translation during early IOMMU startup for those devices. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Lu Baolu --- drivers/iommu/iommu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 59244c744eabd..adef1a37f9311 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -542,8 +542,20 @@ static void iommu_deinit_device(struct device *dev) * Regardless, if a delayed attach never occurred, then the release * should still avoid touching any hardware configuration either. */ - if (!dev->iommu->attach_deferred && ops->release_domain) - ops->release_domain->ops->attach_dev(ops->release_domain, dev); + if (!dev->iommu->attach_deferred && ops->release_domain) { + struct iommu_domain *release_domain =3D ops->release_domain; + + /* + * If the device requires direct mappings then it should not + * be parked on a BLOCKED domain during release as that would + * break the direct mappings. + */ + if (dev->iommu->require_direct && ops->identity_domain && + release_domain =3D=3D ops->blocked_domain) + release_domain =3D ops->identity_domain; + + release_domain->ops->attach_dev(release_domain, dev); + } =20 if (ops->release_device) ops->release_device(dev); --=20 2.43.0