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AJvYcCUCDXGxB/F4yq8KVBEiB4svsqKiNlo1xVTGes4AEp3LVI72h6W06OB+Y8+kLveFFglrjWdiwOtBmYKAlQjP@vger.kernel.org, AJvYcCVgiJlS0ysZbVvLEOBLWmHXng1zNLNp0w0tSr+cAE727r8YKCgAlk9C6ng8G7kEyan5cny13n4GyLsv@vger.kernel.org X-Gm-Message-State: AOJu0YwR7O3taUtJ4RXQ9ywMRZB+UsONE39wcmbigSvEY1lPoc+kVW8+ qaRXZRDrQIqr/Nbkpeq6C0z4owWKz3NCyoiAO/X5e8bV/3u0vpFO X-Google-Smtp-Source: AGHT+IE1+3vDt96wuzJHta3Nkt+aV05zWOrqsajEFRzvGnq1988dsLWPrG80m3LN6mFGflF/nyetBQ== X-Received: by 2002:a05:6870:380d:b0:277:e08a:23a0 with SMTP id 586e51a60fabf-295602fd28cmr7803476fac.41.1731297723750; Sun, 10 Nov 2024 20:02:03 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71a108e29f8sm2121721a34.47.2024.11.10.20.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 20:02:02 -0800 (PST) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 2/3] irqchip: Add the Sophgo SG2042 MSI interrupt controller Date: Mon, 11 Nov 2024 12:01:55 +0800 Message-Id: <8076fe2af9f2b007a42c986ed193ba50ff674bfa.1731296803.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add driver for Sophgo SG2042 MSI interrupt controller. Signed-off-by: Chen Wang --- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sg2042-msi.c | 255 +++++++++++++++++++++++++++++++ 3 files changed, 264 insertions(+) create mode 100644 drivers/irqchip/irq-sg2042-msi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index d82bcab233a1..76a38a4d62eb 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -729,6 +729,14 @@ config MCHP_EIC help Support for Microchip External Interrupt Controller. =20 +config SOPHGO_SG2042_MSI + bool "Sophgo SG2042 MSI controller" + depends on ARCH_SOPHGO || COMPILE_TEST + help + Support for the Sophgo SG2042 MSI Controller. + This on-chip interrupt controller enables MSI sources to be + routed to the primary PLIC controller on SoC. + config SUNPLUS_SP7021_INTC bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST default SOC_SP7021 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e3679ec2b9f7..53617890268a 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -125,4 +125,5 @@ obj-$(CONFIG_WPCM450_AIC) +=3D irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) +=3D irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) +=3D irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) +=3D irq-mchp-eic.o +obj-$(CONFIG_SOPHGO_SG2042_MSI) +=3D irq-sg2042-msi.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) +=3D irq-sp7021-intc.o diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c new file mode 100644 index 000000000000..79449f974ed5 --- /dev/null +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SG2042 MSI Controller + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct sg2042_msi_data { + void __iomem *reg_clr; /* clear reg, see TRM, 10.1.33, GP_INTR0_CLR */ + + u64 doorbell_addr; /* see TRM, 10.1.32, GP_INTR0_SET */ + + u32 irq_first; /* The vector number that MSIs starts */ + u32 num_irqs; /* The number of vectors for MSIs */ + + unsigned long *msi_map; + struct mutex msi_map_lock; /* lock for msi_map */ +}; + +static int sg2042_msi_allocate_hwirq(struct sg2042_msi_data *priv, int num= _req) +{ + int first; + + mutex_lock(&priv->msi_map_lock); + + first =3D bitmap_find_free_region(priv->msi_map, priv->num_irqs, + get_count_order(num_req)); + if (first < 0) { + mutex_unlock(&priv->msi_map_lock); + return -ENOSPC; + } + + mutex_unlock(&priv->msi_map_lock); + + return priv->irq_first + first; +} + +static void sg2042_msi_free_hwirq(struct sg2042_msi_data *priv, + int hwirq, int num_req) +{ + int first =3D hwirq - priv->irq_first; + + mutex_lock(&priv->msi_map_lock); + bitmap_release_region(priv->msi_map, first, get_count_order(num_req)); + mutex_unlock(&priv->msi_map_lock); +} + +static void sg2042_msi_irq_ack(struct irq_data *d) +{ + struct sg2042_msi_data *data =3D irq_data_get_irq_chip_data(d); + int bit_off =3D d->hwirq - data->irq_first; + + writel(1 << bit_off, (unsigned int *)data->reg_clr); + + irq_chip_ack_parent(d); +} + +static void sg2042_msi_irq_compose_msi_msg(struct irq_data *data, + struct msi_msg *msg) +{ + struct sg2042_msi_data *priv =3D irq_data_get_irq_chip_data(data); + + msg->address_hi =3D upper_32_bits(priv->doorbell_addr); + msg->address_lo =3D lower_32_bits(priv->doorbell_addr); + msg->data =3D 1 << (data->hwirq - priv->irq_first); + + pr_debug("%s hwirq[%d]: address_hi[%#x], address_lo[%#x], data[%#x]\n", + __func__, + (int)data->hwirq, msg->address_hi, msg->address_lo, msg->data); +} + +static struct irq_chip sg2042_msi_middle_irq_chip =3D { + .name =3D "SG2042 MSI", + .irq_ack =3D sg2042_msi_irq_ack, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .irq_compose_msi_msg =3D sg2042_msi_irq_compose_msi_msg, +}; + +static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, + unsigned int virq, int hwirq) +{ + struct irq_fwspec fwspec; + struct irq_data *d; + int ret; + + fwspec.fwnode =3D domain->parent->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D hwirq; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + ret =3D irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); + if (ret) + return ret; + + d =3D irq_domain_get_irq_data(domain->parent, virq); + return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING); +} + +static int sg2042_msi_middle_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct sg2042_msi_data *priv =3D domain->host_data; + int hwirq, err, i; + + hwirq =3D sg2042_msi_allocate_hwirq(priv, nr_irqs); + if (hwirq < 0) + return hwirq; + + for (i =3D 0; i < nr_irqs; i++) { + err =3D sg2042_msi_parent_domain_alloc(domain, virq + i, hwirq + i); + if (err) + goto err_hwirq; + + pr_debug("%s: virq[%d], hwirq[%d]\n", + __func__, virq + i, (int)hwirq + i); + + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &sg2042_msi_middle_irq_chip, priv); + } + + return 0; + +err_hwirq: + sg2042_msi_free_hwirq(priv, hwirq, nr_irqs); + irq_domain_free_irqs_parent(domain, virq, i); + + return err; +} + +static void sg2042_msi_middle_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + struct sg2042_msi_data *priv =3D irq_data_get_irq_chip_data(d); + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + sg2042_msi_free_hwirq(priv, d->hwirq, nr_irqs); +} + +static const struct irq_domain_ops pch_msi_middle_domain_ops =3D { + .alloc =3D sg2042_msi_middle_domain_alloc, + .free =3D sg2042_msi_middle_domain_free, +}; + +static int sg2042_msi_init_domains(struct sg2042_msi_data *priv, + struct device_node *node) +{ + struct irq_domain *plic_domain, *middle_domain; + struct device_node *plic_node; + struct fwnode_handle *fwnode =3D of_node_to_fwnode(node); + + if (!of_find_property(node, "interrupt-parent", NULL)) { + pr_err("Can't find interrupt-parent!\n"); + return -EINVAL; + } + + plic_node =3D of_irq_find_parent(node); + if (!plic_node) { + pr_err("Failed to find the PLIC node!\n"); + return -ENXIO; + } + + plic_domain =3D irq_find_host(plic_node); + of_node_put(plic_node); + if (!plic_domain) { + pr_err("Failed to find the PLIC domain\n"); + return -ENXIO; + } + + middle_domain =3D irq_domain_create_hierarchy(plic_domain, 0, priv->num_i= rqs, + fwnode, + &pch_msi_middle_domain_ops, + priv); + if (!middle_domain) { + pr_err("Failed to create the MSI middle domain\n"); + return -ENOMEM; + } + + return 0; +} + +static int sg2042_msi_probe(struct platform_device *pdev) +{ + struct sg2042_msi_data *data; + + data =3D devm_kzalloc(&pdev->dev, sizeof(struct sg2042_msi_data), GFP_KER= NEL); + if (!data) + return -ENOMEM; + + data->reg_clr =3D devm_platform_ioremap_resource_byname(pdev, "clr"); + if (IS_ERR(data->reg_clr)) { + dev_err(&pdev->dev, "Failed to map clear register\n"); + return PTR_ERR(data->reg_clr); + } + + if (of_property_read_u64(pdev->dev.of_node, "sophgo,msi-doorbell-addr", + &data->doorbell_addr)) { + dev_err(&pdev->dev, "Unable to parse MSI doorbell addr\n"); + return -EINVAL; + } + + if (of_property_read_u32(pdev->dev.of_node, "sophgo,msi-base-vec", + &data->irq_first)) { + dev_err(&pdev->dev, "Unable to parse MSI vec base\n"); + return -EINVAL; + } + + if (of_property_read_u32(pdev->dev.of_node, "sophgo,msi-num-vecs", + &data->num_irqs)) { + dev_err(&pdev->dev, "Unable to parse MSI vec number\n"); + return -EINVAL; + } + + mutex_init(&data->msi_map_lock); + + data->msi_map =3D bitmap_zalloc(data->num_irqs, GFP_KERNEL); + if (!data->msi_map) + return -ENOMEM; + + return sg2042_msi_init_domains(data, pdev->dev.of_node); +} + +static const struct of_device_id sg2042_msi_of_match[] =3D { + { .compatible =3D "sophgo,sg2042-msi" }, + {} +}; + +static struct platform_driver sg2042_msi_driver =3D { + .driver =3D { + .name =3D "sg2042-msi", + .of_match_table =3D of_match_ptr(sg2042_msi_of_match), + }, + .probe =3D sg2042_msi_probe, +}; +builtin_platform_driver(sg2042_msi_driver); --=20 2.34.1