From nobody Fri Sep 20 12:34:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FD75C001DC for ; Sat, 29 Jul 2023 13:56:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231480AbjG2N4D (ORCPT ); Sat, 29 Jul 2023 09:56:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231483AbjG2Nz5 (ORCPT ); Sat, 29 Jul 2023 09:55:57 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 445DE1BC9; Sat, 29 Jul 2023 06:55:50 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qPkPr-0001I0-14; Sat, 29 Jul 2023 13:55:31 +0000 Date: Sat, 29 Jul 2023 14:55:15 +0100 From: Daniel Golle To: Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next] net: ethernet: mtk_eth_soc: support per-flow accounting on MT7988 Message-ID: <801c89963e95e5ce8f1ab7dbda894dd9da0125cc.1690638748.git.daniel@makrotopia.org> MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NETSYS_V3 uses 64 bits for each counters while older SoCs were using 48 bits for each counter. Support reading per-flow byte and package counters on NETSYS_V3. Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + drivers/net/ethernet/mediatek/mtk_ppe.c | 18 ++++++++++++++---- drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 2 ++ 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index 05be702f19c5e..1b89f800f6dff 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -5064,6 +5064,7 @@ static const struct mtk_soc_data mt7988_data =3D { .version =3D 3, .offload_version =3D 2, .hash_offset =3D 4, + .has_accounting =3D true, .foe_entry_size =3D MTK_FOE_ENTRY_V3_SIZE, .txrx =3D { .txd_size =3D sizeof(struct mtk_tx_dma_v2), diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet= /mediatek/mtk_ppe.c index bf1ecb0c1c109..1ec508bb206bf 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c @@ -107,10 +107,20 @@ static int mtk_mib_entry_read(struct mtk_ppe *ppe, u1= 6 index, u64 *bytes, u64 *p cnt_r1 =3D readl(ppe->base + MTK_PPE_MIB_SER_R1); cnt_r2 =3D readl(ppe->base + MTK_PPE_MIB_SER_R2); =20 - byte_cnt_low =3D FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); - byte_cnt_high =3D FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); - pkt_cnt_low =3D FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); - pkt_cnt_high =3D FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); + if (mtk_is_netsys_v3_or_greater(ppe->eth)) { + /* 64 bit for each counter */ + bytes_cnt_low =3D cnt_r0; + bytes_cnt_high =3D cnt_r1; + pkt_cnt_low =3D cnt_r2; + pkt_cnt_high =3D readl(ppe->base + MTK_PPE_MIB_SER_R3); + } else { + /* 48 bit for each counter */ + byte_cnt_low =3D FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); + byte_cnt_high =3D FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); + pkt_cnt_low =3D FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); + pkt_cnt_high =3D FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); + } + *bytes =3D ((u64)byte_cnt_high << 32) | byte_cnt_low; *packets =3D (pkt_cnt_high << 16) | pkt_cnt_low; =20 diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/eth= ernet/mediatek/mtk_ppe_regs.h index a2e61b3eb006d..3ce088eef0efd 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h @@ -163,6 +163,8 @@ enum { #define MTK_PPE_MIB_SER_R2 0x348 #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0) =20 +#define MTK_PPE_MIB_SER_R3 0x34c + #define MTK_PPE_MIB_CACHE_CTL 0x350 #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) --=20 2.41.0