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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT010.mail.protection.outlook.com (10.13.172.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5273.14 via Frontend Transport; Mon, 23 May 2022 16:56:39 +0000 Received: from beas.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 23 May 2022 11:56:31 -0500 From: Wyes Karny To: CC: , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 1/3] x86: Handle idle=nomwait cmdline properly for x86_idle Date: Mon, 23 May 2022 22:25:49 +0530 Message-ID: <7e5a66c4d383652c89a0b5ec0f57e0a95902f810.1653324016.git-series.wyes.karny@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 343c36a5-7654-42d2-fc97-08da3cdd3466 X-MS-TrafficTypeDiagnostic: MN2PR12MB3069:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2022 16:56:39.0012 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 343c36a5-7654-42d2-fc97-08da3cdd3466 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3069 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When kernel is booted with idle=3Dnomwait do not use MWAIT as the default idle state. If the user boots the kernel with idle=3Dnomwait, it is a clear direction to not use mwait as the default idle state. However, the current code does not take this into consideration while selecting the default idle state on x86. This patch fixes it by checking for the idle=3Dnomwait boot option in prefer_mwait_c1_over_halt(). Also update the documentation around idle=3Dnomwait appropriately. Signed-off-by: Wyes Karny --- Changes in v4: - Update documentation around idle=3Dnomwait - Rename patch subject Documentation/admin-guide/pm/cpuidle.rst | 15 +++++++++------ arch/x86/kernel/process.c | 6 +++++- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/admin-guide/pm/cpuidle.rst b/Documentation/admin= -guide/pm/cpuidle.rst index aec2cd2aaea7..19754beb5a4e 100644 --- a/Documentation/admin-guide/pm/cpuidle.rst +++ b/Documentation/admin-guide/pm/cpuidle.rst @@ -612,8 +612,8 @@ the ``menu`` governor to be used on the systems that us= e the ``ladder`` governor by default this way, for example. =20 The other kernel command line parameters controlling CPU idle time managem= ent -described below are only relevant for the *x86* architecture and some of -them affect Intel processors only. +described below are only relevant for the *x86* architecture and references +to ``intel_idle`` affect Intel processors only. =20 The *x86* architecture support code recognizes three kernel command line options related to CPU idle time management: ``idle=3Dpoll``, ``idle=3Dhal= t``, @@ -635,10 +635,13 @@ idle, so it very well may hurt single-thread computat= ions performance as well as energy-efficiency. Thus using it for performance reasons may not be a goo= d idea at all.] =20 -The ``idle=3Dnomwait`` option disables the ``intel_idle`` driver and causes -``acpi_idle`` to be used (as long as all of the information needed by it is -there in the system's ACPI tables), but it is not allowed to use the -``MWAIT`` instruction of the CPUs to ask the hardware to enter idle states. +The ``idle=3Dnomwait`` option prevents the use of ``MWAIT`` instruction of +the CPU to enter idle states. When this option is used, the ``acpi_idle`` +driver will use the ``HLT`` instruction instead of ``MWAIT``. On systems +running Intel processors, this option disables the ``intel_idle`` driver +and forces the use of the ``acpi_idle`` driver instead. Note that in either +case, ``acpi_idle`` driver will function only if all the information needed +by it is in the system's ACPI tables. =20 In addition to the architecture-level kernel command line options affectin= g CPU idle time management, there are parameters affecting individual ``CPUIdle`` diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b370767f5b19..4e0178b066c5 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -824,6 +824,10 @@ static void amd_e400_idle(void) */ static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) { + /* User has disallowed the use of MWAIT. Fallback to HALT */ + if (boot_option_idle_override =3D=3D IDLE_NOMWAIT) + return 0; + if (c->x86_vendor !=3D X86_VENDOR_INTEL) return 0; =20 @@ -932,7 +936,7 @@ static int __init idle_setup(char *str) } else if (!strcmp(str, "nomwait")) { /* * If the boot option of "idle=3Dnomwait" is added, - * it means that mwait will be disabled for CPU C2/C3 + * it means that mwait will be disabled for CPU C1/C2/C3 * states. In such case it won't touch the variable * of boot_option_idle_override. */ --=20 git-series 0.9.1