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Sat, 28 Jun 2025 00:42:52 -0700 From: Nicolin Chen To: , , , , , , CC: , , , , , , , , Subject: [PATCH RFC v2 4/4] pci: Suspend iommu function prior to resetting a device Date: Sat, 28 Jun 2025 00:42:42 -0700 Message-ID: <7889db2790263640c6e9bb98956c3a3d55b87ee6.1751096303.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|MW4PR12MB7263:EE_ X-MS-Office365-Filtering-Correlation-Id: c910519f-fe3e-409c-dceb-08ddb6176bde X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?HJ8OIdtPdaAWJ1ho3LhFz4SrMh5HgtsgFzvxnxY2YOlT4Pc/tr4c3ZqarIqm?= =?us-ascii?Q?pSf3W3TmHFLRVJ+MOwV+TJbDCidCPSihZVXvm9pBMoC4Z5PNUtJESj12xvu4?= =?us-ascii?Q?rlwpB/lPtMKQGn12aRzC+hVFe+peyMI/d4GCvDxmeSlyOmSghRAgxJgAT3Cy?= =?us-ascii?Q?Kb+YDeshlGNfZDvAeQnwwcpvF11zwoRMMznGbY6z++FP5dmB0+WgkeMd/R/U?= =?us-ascii?Q?B6BTAArOachcUP+fqNW3kToPWIdII2yKkWJnWZJTtVzb69kcr+9A2RF1vgNl?= =?us-ascii?Q?PA9ULG+CpYP1HeNrLfgZVSQkIalADDfT38RRyQWZ6wjAdBf7qRzjO4AnCkwB?= =?us-ascii?Q?NhA93oXNkEvKod5x/3OcENs5P96jNGIijg4d0z4olTKFwtS4bB+832Hspiha?= =?us-ascii?Q?8xQFwlBE2nfOxHea7DwNJC4UFEFhfBkd9dqgPfmvo2Xd81H9ld2SmUxGskFB?= =?us-ascii?Q?z5psXrtt4vAKnqL3r972wZY8jRc/KFDVs4KI0HBy3V8m/qGT/MzcJauxq81m?= =?us-ascii?Q?13zwloBB+ugII1l7rXt3fpvlDz8owENWvAlaZ6Kv6qC0tzeELnPa7dkUXe1Q?= =?us-ascii?Q?Hmint8QYO/B9WexT6cBPOJ7FGNFzZbRuzXpL+Wh+1LKOhcBY6k7lPidWOumq?= =?us-ascii?Q?kZgGtkLuxaneOUTuEPE6Bkn90z7ntEgIN6wyNJkHKCf0stcMN+lNTHOg2OSg?= =?us-ascii?Q?R7vYWqF4Ehlql4fIHj/LJaULXCxfuGYcTleubWYgObhuUu1P5aSiBrtT1w7x?= =?us-ascii?Q?JM7Saf6XJ2Uye0IR6Vglc9FnfQHl+5KNHlQ9dH6+mMMZB6XEeeUm4vX6DTSx?= =?us-ascii?Q?dUAk+9L341BAJrWtEDexVbImG0S/1vMrCn0O4COVPwsKXuSRafOTcbPvcAI4?= =?us-ascii?Q?9ettNIgaBwCbyWjI7Zyi0XEDIhNJmU5LdCwLjNFT+wUWrLlkN1jBBuaepgYK?= =?us-ascii?Q?R/NdWkcCOBPVBsmBDZb7bnv6O2Oc5b6QC32bQ6+qFP6gUxKTntJU23vUAVhs?= =?us-ascii?Q?pNv7yi0mAO4b6fKikHmuCBwOHeIKgP8BUdgNCjNFwm26aChVqdnAvnOEpJ0T?= =?us-ascii?Q?8F7pmPkVfwmhTHE1kjSW0JhBtT6OWKDJJi7Cv6D0drzpP4aexTbmS+fEo2Qs?= =?us-ascii?Q?QllNf+Y/8Jz4ZaV00WVH/SzSk8evld7nUvohtN8M4Igk4t8Re7PT6MdZa3y3?= =?us-ascii?Q?tCJQcf5vvsPdS1Ou1dCcNgHuoxElHjyNsY5zKp3qYo2/GKeuF6hckTrIvaLb?= =?us-ascii?Q?YvRWYoJSaJPvbZjSvcBhr7Y5lk4th4bnDbjgPpfbVNSQdkuCzZXs7AW1+QLX?= =?us-ascii?Q?96ZcjO7OUC2Q0xyS9iGK8fK/h0EraEkq9qBW5sggSKhCNPSYnxnGwyl0HI4Y?= =?us-ascii?Q?xLTnIGeXvt31DDKqy0lf2rawYFd36a5V/8I2xM4wlvTXLhVA/2G3XzrulKm7?= =?us-ascii?Q?kyc0TjQG4aqffH+9M5Ohpio6/4CzmQn80Wb9X1tIEB+bUZs1p0c0dEJ/fWl+?= =?us-ascii?Q?Af3hYUNmP9myBpiQV5tCBdJvItWOiRCA0n61?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2025 07:43:06.5277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c910519f-fe3e-409c-dceb-08ddb6176bde X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7263 Content-Type: text/plain; charset="utf-8" PCIe permits a device to ignore ATS invalidation TLPs, while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out: e.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The PCIe spec in sec 10.3.1 IMPLEMENTATION NOTE recommends to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. Now iommu_dev_reset_prepare/done() helpers are introduced for this matter. Use them in all the existing reset functions, which will attach the device to an IOMMU_DOMAIN_BLOCKED during a reset, so as to allow IOMMU driver to: - invoke pci_disable_ats() and pci_enable_ats() respectively - wait for all ATS invalidations to complete - stop issuing new ATS invalidations - fence any incoming ATS queries Add a warning if ATS isn't disabled, in which case IOMMU driver should fix itself to disable ATS following the design in iommu_dev_reset_prepare(). Signed-off-by: Nicolin Chen --- drivers/pci/pci-acpi.c | 21 ++++++++++- drivers/pci/pci.c | 84 +++++++++++++++++++++++++++++++++++++++--- drivers/pci/quirks.c | 27 +++++++++++++- 3 files changed, 124 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index b78e0e417324..727957f193ca 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -974,6 +975,7 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) { acpi_handle handle =3D ACPI_HANDLE(&dev->dev); + int ret =3D 0; =20 if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; @@ -981,12 +983,27 @@ int pci_dev_acpi_reset(struct pci_dev *dev, bool prob= e) if (probe) return 0; =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + /* Something wrong with the iommu driver that failed to disable ATS */ + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS. ATS invalidation may time out\n"); + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { pci_warn(dev, "ACPI _RST failed\n"); - return -ENOTTY; + ret =3D -ENOTTY; } =20 - return 0; + iommu_dev_reset_done(&dev->dev); + return ret; } =20 bool acpi_pci_power_manageable(struct pci_dev *dev) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e9448d55113b..ddb7a10ef500 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -4518,13 +4519,30 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); */ int pcie_flr(struct pci_dev *dev) { + int ret =3D 0; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing func= tion level reset anyway\n"); =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + * Have to call it after waiting for pending DMA transaction. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + /* Something wrong with the iommu driver that failed to disable ATS */ + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS. ATS invalidation may time out\n"); + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within @@ -4533,7 +4551,11 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); =20 - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + +done: + iommu_dev_reset_done(&dev->dev); + return ret; } EXPORT_SYMBOL_GPL(pcie_flr); =20 @@ -4561,6 +4583,7 @@ EXPORT_SYMBOL_GPL(pcie_reset_flr); =20 static int pci_af_flr(struct pci_dev *dev, bool probe) { + int ret =3D 0; int pos; u8 cap; =20 @@ -4587,10 +4610,25 @@ static int pci_af_flr(struct pci_dev *dev, bool pro= be) PCI_AF_STATUS_TP << 8)) pci_err(dev, "timed out waiting for pending transaction; performing AF f= unction level reset anyway\n"); =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + * Have to call it after waiting for pending DMA transaction. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + /* Something wrong with the iommu driver that failed to disable ATS */ + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS. ATS invalidation may time out\n"); + pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, @@ -4600,7 +4638,11 @@ static int pci_af_flr(struct pci_dev *dev, bool prob= e) */ msleep(100); =20 - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + +done: + iommu_dev_reset_done(&dev->dev); + return ret; } =20 /** @@ -4621,6 +4663,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) static int pci_pm_reset(struct pci_dev *dev, bool probe) { u16 csr; + int ret; =20 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4635,6 +4678,20 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) if (dev->current_state !=3D PCI_D0) return -EINVAL; =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + /* Something wrong with the iommu driver that failed to disable ATS */ + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS. ATS invalidation may time out\n"); + csr &=3D ~PCI_PM_CTRL_STATE_MASK; csr |=3D PCI_D3hot; pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); @@ -4645,7 +4702,9 @@ static int pci_pm_reset(struct pci_dev *dev, bool pro= be) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); =20 - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + iommu_dev_reset_done(&dev->dev); + return ret; } =20 /** @@ -5100,6 +5159,20 @@ static int cxl_reset_bus_function(struct pci_dev *de= v, bool probe) if (rc) return -ENOTTY; =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + rc =3D iommu_dev_reset_prepare(&dev->dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU\n"); + return rc; + } + + /* Something wrong with the iommu driver that failed to disable ATS */ + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS. ATS invalidation may time out\n"); + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { val =3D reg; } else { @@ -5114,6 +5187,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev= , bool probe) pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, reg); =20 + iommu_dev_reset_done(&dev->dev); return rc; } =20 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d7f4ee634263..7a66c01392d9 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -21,6 +21,7 @@ #include #include /* isa_dma_bridge_buggy */ #include +#include #include #include #include @@ -4223,6 +4224,30 @@ static const struct pci_dev_reset_methods pci_dev_re= set_methods[] =3D { { 0 } }; =20 +static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, + const struct pci_dev_reset_methods *i) +{ + int ret; + + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + /* Something wrong with the iommu driver that failed to disable ATS */ + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS. ATS invalidation may time out\n"); + + ret =3D i->reset(dev, probe); + iommu_dev_reset_done(&dev->dev); + return ret; +} + /* * These device-specific reset methods are here rather than in a driver * because when a host assigns a device to a guest VM, the host may need @@ -4237,7 +4262,7 @@ int pci_dev_specific_reset(struct pci_dev *dev, bool = probe) i->vendor =3D=3D (u16)PCI_ANY_ID) && (i->device =3D=3D dev->device || i->device =3D=3D (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return __pci_dev_specific_reset(dev, probe, i); } =20 return -ENOTTY; --=20 2.43.0