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Mon, 14 Apr 2025 21:58:18 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 08/11] iommu/arm-smmu-v3: Use vSMMU helpers for S2 and ATC invalidations Date: Mon, 14 Apr 2025 21:57:43 -0700 Message-ID: <771891ae889f880832c70d5ed895802732138478.1744692494.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D1:EE_|DM6PR12MB4251:EE_ X-MS-Office365-Filtering-Correlation-Id: 609de5aa-7a7a-4c8e-d990-08dd7bda2cbd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?bHUQHTHQ7HBnhqgajtc1xpFa9vBPli7JOcocaNBg6tAKOL/OOsbgBjCrbNdv?= =?us-ascii?Q?lkakYgOeNUy0a6AP0gWjQu13Wo3G6kEgtS3cQEP3sEcI1OZv5PR71zDQCuxY?= =?us-ascii?Q?WYIHzo7gpUcUcXEnUbCAImIDhA0w6os677YzN4mfk5qzrKXssC3ES7SLA41q?= =?us-ascii?Q?kthl4yMeIWEQrh57wB9r4jXsqo8lhicq/7gV6MqhU/mfAjGfo6o+Hod2JcBB?= =?us-ascii?Q?lHyBN5NWPvzjf/OT0fA/M9ki7qvjpHSu7oK6pHsxKpSU2Ympd8PRyoXg27Tq?= =?us-ascii?Q?vUzyOF8QUh13CWzAZ2QIhmaL7HXftR4a4U+bJ/YqK4QXrBugrHUHqCMLcDlP?= =?us-ascii?Q?35+NqERrG+DObsUBPkBb7Adh+Z6+1hlXrAW4iB0WC2FyiaGe3AjPc5g9MwaI?= =?us-ascii?Q?IMR+8P8n5JZGUcJXYr3X7as8yxR5Di9V8q5KDU7wS1Fk83dlBHBEHA1e+gqF?= =?us-ascii?Q?Q43LSDm17+R+kVbJWMbxLDBResZvmUtuRcCC8MK9D1b2KBCNznRtY/j+I/3E?= =?us-ascii?Q?SjEFHu2jyoTm1gNE5ij/0BNsT9Veed033ZfTH57em46vnP/MScgCG/48VfGj?= =?us-ascii?Q?4K4uW3B8voy4Ex1ABnyZ1VD4dHyGUtf+tvcunbPN5V2HyT5+WsjaxsRxsN2t?= =?us-ascii?Q?WliBcNzhFZEqEelEsN1IwKsL3EGs2jmcGisqRgcZ6vQHJOpyVr0rKhNzBcCI?= =?us-ascii?Q?cE9SUrIWgJ+dOpXXUL4SH+nuKVRUI9bUckrlc0ITG5mPCI6rAcQ3k0GEvp4f?= =?us-ascii?Q?FV8j/dNkeJL5EHq0D2FJ+oJoZSPmEIHFsHQ68GT6xI0ndV/lZNf7qqUswyLt?= =?us-ascii?Q?B6vFab1awxDbibJYKaTk1iBoaP8PAhif5Jng+l8GvR3a2dBY8RpFbV7iWzdq?= =?us-ascii?Q?oCGhWpHzroF9EijHllqZHMMRAZkyeSx6WXZxUuG1BdIwM+ta2iVXqB6lbBuI?= =?us-ascii?Q?wjKY19wt/HG0HitquyywqslWM7naq0QZjScUlZf8E4W5dPxtrP5e/oCqkY9u?= =?us-ascii?Q?4f1zlSkg510w38BoJtT/un95cFMKGBdrwFjsJXn0v4A6jbTflMTOXI0xT6jg?= =?us-ascii?Q?GlRu4ywWp/fpkFcyQX1R48ILi2NuF9q6PfD1FikCmm1hu+qUHtAMAEs7fLMp?= =?us-ascii?Q?tfKib6L6QVfp2pNpkF0JCBtyG7ZsOpuXHQCcBZfBkDSLMAS5seeEziP40rIN?= =?us-ascii?Q?GnxrPD5mvFENQsL3mb6pO4KVXbfCxv2azjt0ZLf1YAefqRyHTt6zy556drIT?= =?us-ascii?Q?WxURMCwQ8K4f/bz3B3/6ODom164WdMlkKwEcleH7WVIgB+cG63U+57NsHOpG?= =?us-ascii?Q?UPT8DdhwjStrreTUgt7y0GQmKC6qjgAXvmehizRmOhuUZU/bLTlgl8RtdSBe?= =?us-ascii?Q?OcNmhd2T3vSIUf2VBi9H1ShZmcuRPlERO/ZnRD8JkQqxImcEJbAyLHM+lNJn?= =?us-ascii?Q?ZaXCc16DtQevicbqWRTnODwsDTwSxa1ldWvgAW8SvmftvlTBmuoxLiYA1oOI?= =?us-ascii?Q?7/DFybEwZ1Hq/SL+1sg5hjOO7QbGMZEz9LZM?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:33.9111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 609de5aa-7a7a-4c8e-d990-08dd7bda2cbd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4251 Content-Type: text/plain; charset="utf-8" Now the driver can do a per-vSMMU S2 cache and ATC invalidations, given a pair of arm_smmu_s2_parent_* helpers. Use them in the arm_smmu_tlb_inv_* functions, replacing the existing per-domain invalidations. This also requires to add/remove the device onto/from the ats_devices list of the vSMMU. Note that this is shifting away from the nested_ats_flush in the struct arm_smmu_master_domain, which now became a dead code, requiring a cleanup. Move the arm_vsmmu_attach_prepare() call in arm_smmu_attach_prepare(), out of the !IOMMU_DOMAIN_NESTED routine, so that it doesn't need to revert the arm_vsmmu_attach_prepare(), which wouldn't only require a simple kfree(). All of these have to be done in one single patch, so nothing is broken. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 27 ++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 45 +++++++++---------- 3 files changed, 55 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index d130d723cc33..c9b9c7921bee 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1104,6 +1104,8 @@ int arm_vsmmu_attach_prepare(struct arm_smmu_attach_s= tate *state, struct arm_vsmmu *vsmmu); void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master); +void arm_vsmmu_remove_ats_device(struct arm_vsmmu *vsmmu, + struct arm_smmu_master *master); int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); =20 void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent); @@ -1130,6 +1132,11 @@ arm_smmu_master_clear_vmaster(struct arm_smmu_master= *master) { } =20 +static inline void arm_vsmmu_remove_ats_device(struct arm_vsmmu *vsmmu, + struct arm_smmu_master *master) +{ +} + static inline int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaste= r, u64 *evt) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 4730ff56cf04..491f2b88e30b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -182,11 +182,13 @@ static void arm_smmu_make_nested_domain_ste( int arm_vsmmu_attach_prepare(struct arm_smmu_attach_state *state, struct arm_vsmmu *vsmmu) { + struct arm_smmu_master *master =3D state->master; struct arm_smmu_vmaster *vmaster; + unsigned long flags; unsigned long vsid; int ret; =20 - iommu_group_mutex_assert(state->master->dev); + iommu_group_mutex_assert(master->dev); =20 ret =3D iommufd_viommu_get_vdev_id(&vsmmu->core, state->master->dev, &vsid); @@ -200,6 +202,12 @@ int arm_vsmmu_attach_prepare(struct arm_smmu_attach_st= ate *state, vmaster->vsid =3D vsid; state->vmaster =3D vmaster; =20 + if (state->ats_enabled) { + spin_lock_irqsave(&vsmmu->ats_devices.lock, flags); + list_add(&master->devices_elm, &vsmmu->ats_devices.list); + spin_unlock_irqrestore(&vsmmu->ats_devices.lock, flags); + } + return 0; } =20 @@ -220,6 +228,23 @@ void arm_smmu_master_clear_vmaster(struct arm_smmu_mas= ter *master) arm_smmu_attach_commit_vmaster(&state); } =20 +void arm_vsmmu_remove_ats_device(struct arm_vsmmu *vsmmu, + struct arm_smmu_master *master) +{ + struct arm_smmu_cmdq_ent cmd =3D { .opcode =3D CMDQ_OP_ATC_INV }; + struct arm_smmu_cmdq_batch cmds; + unsigned long flags; + + arm_smmu_cmdq_batch_init(vsmmu->smmu, &cmds, &cmd); + + spin_lock_irqsave(&vsmmu->ats_devices.lock, flags); + list_del(&master->devices_elm); + arm_vsmmu_cmdq_batch_add_atc_inv(vsmmu, master, &cmds, &cmd); + spin_unlock_irqrestore(&vsmmu->ats_devices.lock, flags); + + arm_smmu_cmdq_batch_submit(vsmmu->smmu, &cmds); +} + static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, struct device *dev) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index df87880e2a29..483ef9e2c6b7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2255,6 +2255,10 @@ static void arm_smmu_tlb_inv_context(void *cookie) * insertion to guarantee those are observed before the TLBI. Do be * careful, 007. */ + + if (smmu_domain->nest_parent) + return arm_smmu_s2_parent_tlb_inv_domain(smmu_domain); + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); else @@ -2342,6 +2346,11 @@ static void arm_smmu_tlb_inv_range_domain(unsigned l= ong iova, size_t size, }, }; =20 + if (smmu_domain->nest_parent) { + return arm_smmu_s2_parent_tlb_inv_range(smmu_domain, iova, size, + granule, leaf); + } + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; @@ -2353,15 +2362,6 @@ static void arm_smmu_tlb_inv_range_domain(unsigned l= ong iova, size_t size, __arm_smmu_tlb_inv_range(smmu_domain->smmu, &cmd, iova, size, granule, &smmu_domain->domain); =20 - if (smmu_domain->nest_parent) { - /* - * When the S2 domain changes all the nested S1 ASIDs have to be - * flushed too. - */ - cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; - arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); - } - /* * Unfortunately, this can't be leaf-only since we may have * zapped an entire table. @@ -2765,8 +2765,11 @@ static void arm_smmu_remove_master_domain(struct arm= _smmu_master *master, if (!smmu_domain) return; =20 - if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) - nested_ats_flush =3D to_smmu_nested_domain(domain)->enable_ats; + if (domain->type =3D=3D IOMMU_DOMAIN_NESTED && + to_smmu_nested_domain(domain)->enable_ats) { + return arm_vsmmu_remove_ats_device( + to_smmu_nested_domain(domain)->vsmmu, master); + } =20 spin_lock_irqsave(&smmu_domain->devices_lock, flags); master_domain =3D arm_smmu_find_master_domain(smmu_domain, master, ssid, @@ -2837,20 +2840,17 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_= state *state, arm_smmu_ats_supported(master); } =20 - if (smmu_domain) { - if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { - ret =3D arm_vsmmu_attach_prepare( - state, - to_smmu_nested_domain(new_domain)->vsmmu); - if (ret) - return ret; - } + if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { + struct arm_smmu_nested_domain *nested_domain =3D + to_smmu_nested_domain(new_domain); =20 + ret =3D arm_vsmmu_attach_prepare(state, nested_domain->vsmmu); + if (ret) + return ret; + } else if (smmu_domain) { master_domain =3D kzalloc(sizeof(*master_domain), GFP_KERNEL); - if (!master_domain) { - kfree(state->vmaster); + if (!master_domain) return -ENOMEM; - } master_domain->master =3D master; master_domain->ssid =3D state->ssid; if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) @@ -2877,7 +2877,6 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); kfree(master_domain); - kfree(state->vmaster); return -EINVAL; } =20 --=20 2.43.0