From nobody Wed Dec 17 05:55:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B5BCEE49A0 for ; Wed, 23 Aug 2023 09:45:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231971AbjHWJpX (ORCPT ); Wed, 23 Aug 2023 05:45:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229786AbjHWJoM (ORCPT ); Wed, 23 Aug 2023 05:44:12 -0400 Received: from jari.cn (unknown [218.92.28.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 72E7ACFE for ; Wed, 23 Aug 2023 02:43:01 -0700 (PDT) Received: from chenxuebing$jari.cn ( [125.70.163.142] ) by ajax-webmail-localhost.localdomain (Coremail) ; Wed, 23 Aug 2023 17:42:36 +0800 (GMT+08:00) X-Originating-IP: [125.70.163.142] Date: Wed, 23 Aug 2023 17:42:36 +0800 (GMT+08:00) X-CM-HeaderCharset: UTF-8 From: "XueBing Chen" To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amdgpu/sdma4: Clean up errors in sdma_v4_0.c X-Priority: 3 X-Mailer: Coremail Webmail Server Version 2023.1-cmXT6 build 20230419(ff23bf83) Copyright (c) 2002-2023 www.mailtech.cn mispb-4e503810-ca60-4ec8-a188-7102c18937cf-zhkzyfz.cn Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Message-ID: <762fb7bf.629.18a21c6446a.Coremail.chenxuebing@jari.cn> X-Coremail-Locale: zh_CN X-CM-TRANSID: AQAAfwDnhD+M1OVkJHCQAA--.451W X-CM-SenderInfo: hfkh05pxhex0nj6mt2flof0/1tbiAQAMCmTkgo0AVgALsV X-Coremail-Antispam: 1Ur529EdanIXcx71UUUUU7IcSsGvfJ3iIAIbVAYjsxI4VWxJw CS07vEb4IE77IF4wCS07vE1I0E4x80FVAKz4kxMIAIbVAFxVCaYxvI4VCIwcAKzIAtYxBI daVFxhVjvjDU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line ERROR: spaces required around that '?' (ctx:VxW) ERROR: space required before the open parenthesis '(' Signed-off-by: XueBing Chen --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v4_0.c index cd37f45e01a1..cfcd15f77a89 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -152,8 +152,7 @@ static const struct soc15_reg_golden golden_settings_sd= ma0_4_2_init[] =3D { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xffffff= f0, 0x00403000), }; =20 -static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =3D -{ +static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =3D { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x0283= 1f07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100= ), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00= 004002), @@ -213,20 +212,17 @@ static const struct soc15_reg_golden golden_settings_= sdma1_4_2[] =3D { SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x000= 10001), }; =20 -static const struct soc15_reg_golden golden_settings_sdma_rv1[] =3D -{ +static const struct soc15_reg_golden golden_settings_sdma_rv1[] =3D { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00= 000002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f,= 0x00000002) }; =20 -static const struct soc15_reg_golden golden_settings_sdma_rv2[] =3D -{ +static const struct soc15_reg_golden golden_settings_sdma_rv2[] =3D { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00= 003001), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f,= 0x00003001) }; =20 -static const struct soc15_reg_golden golden_settings_sdma_arct[] =3D -{ +static const struct soc15_reg_golden golden_settings_sdma_arct[] =3D { SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x0283= 1f07), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00= 004002), SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f,= 0x00004002), @@ -1100,7 +1096,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device= *adev, unsigned int i) wptr_poll_cntl =3D RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); wptr_poll_cntl =3D REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, - F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); + F32_POLL_ENABLE, amdgpu_sriov_vf(adev) ? 1 : 0); WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); =20 /* enable DMA RB */ @@ -1186,7 +1182,7 @@ static void sdma_v4_0_page_resume(struct amdgpu_devic= e *adev, unsigned int i) wptr_poll_cntl =3D RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); wptr_poll_cntl =3D REG_SET_FIELD(wptr_poll_cntl, SDMA0_PAGE_RB_WPTR_POLL_CNTL, - F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); + F32_POLL_ENABLE, amdgpu_sriov_vf(adev) ? 1 : 0); WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); =20 /* enable DMA RB */ @@ -1246,7 +1242,7 @@ static void sdma_v4_1_init_power_gating(struct amdgpu= _device *adev) /* Configure switch time for hysteresis purpose. Use default right now */ data &=3D ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; data |=3D (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_D= URATION_TIME_MASK); - if(data !=3D def) + if (data !=3D def) WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); } =20 --=20 2.17.1