From nobody Fri Apr 10 02:40:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93E2A351C12; Wed, 4 Mar 2026 17:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644303; cv=none; b=ferknjjLovnfEMx9HuolXkBYlZB6bVL7qCpCZ9uWfIDKgh3GH29uSfWOOFb22axZbIYS5+tErSLMfyFOsGDStGr/YSyKizbOa5ZV8S6PlvTZ6kJGsGROLlFuauBPOq+W0BFnN5UIcmdWaZsezZ1X3C/sJ7LI+RS6akeNyVE1x4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644303; c=relaxed/simple; bh=kU0ohruI6QlSvO91Wx+ILqw+so74xs/j5/KqV3/OHSM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n8R5cIpEzBEeAYpKLwuipVInvsdTOEiHMCJcWj2l8qiuc4VuCXa1EysJxM5sYSnCQBtM2su2PuQy2EyBE5eMtcALJlNgkOcCsBIDB1fTd9BKdfzrrAeoNnQ6ULFO/d/b1B5YCmBVk3xkro2MX9dHf5EQMKMiVjurkjC2u4SM5HQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1085C2BCB1; Wed, 4 Mar 2026 17:11:38 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 6/7] arm64: tegra: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:03 +0100 Message-ID: <7503b501a7f587c1d627245af89254d6052c4f20.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 850c473235e367ac..24ee589396cb18b4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4083,7 +4083,7 @@ gic: interrupt-controller@f400000 { reg =3D <0x0 0x0f400000 0x0 0x010000>, /* GICD */ <0x0 0x0f440000 0x0 0x200000>; /* GICR */ interrupt-parent =3D <&gic>; - interrupts =3D ; + interrupts =3D ; =20 #redistributor-regions =3D <1>; #interrupt-cells =3D <3>; @@ -5869,10 +5869,10 @@ tj-thermal { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; interrupt-parent =3D <&gic>; always-on; }; --=20 2.43.0