From nobody Fri Dec 19 20:52:41 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E3AB2EFDAD for ; Wed, 3 Dec 2025 23:01:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764802907; cv=none; b=DqEqfXaSW0ZZxydgpHnr//9Y+r8Kz4ipcj+CchWbORZ48RCt17FQ2DquLW8sfqca/x+abOrEYIPaq71/GVkzdhR5YktmlcdFPno7ta7IuxETAlghruG+YXcsfmrH3WvfypIFBRxcIK9G7zQ7Meao90BbtEmbg2ZH1AORZqaQMHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764802907; c=relaxed/simple; bh=UY2I5n5Zb5eoLU5mFytvpnggFlTCSd5WOZCBICo1NK0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ss76k4YY8rB/Z6uAGDFyQbUZ7bARhHHFMR8yOxKyMTjDj6HDUJk3fTrjyBpd8eZwWLWJd6uE+i5j5z2Y9c/kkgK7AnD0FSS5RcyHMwddwez0X8IBpyAwZBkh9Vkri2qy0caEGEQrs66nsLD9/pRtuqh/ensvo0F7AVsRu2xo2+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=b/WFlJ1d; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="b/WFlJ1d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764802904; x=1796338904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UY2I5n5Zb5eoLU5mFytvpnggFlTCSd5WOZCBICo1NK0=; b=b/WFlJ1dlftZ7EAiu5bb8CTSjdtBeseHX8isQ4Wht5vD1dxWm6RURFOT R1B3Vg98GKNKQd2LzX3IPnNH9KdzkcCltvIyuRjvzvHEAhFOFxsI/nNCA UEadn+0Fte3u19UFuKUeR+zfOfQY/nrc24OBpPT4wpQKXE96Ne4Zzhez9 CGKthr3Nhi0su6EqgFcgXSic3+e2vAZwxOJETpVdCkTcXOxPoH3AQRibc 89EqfPOQ7c13HxarJn7Y8fuv5oRcK9m2z4cMXZ93jLuPQkW6wM0YzTFzA la772T94DglzvBNsM6aU73BVVoFLW1MUMY65Xa6wwGE8bwa6iEUdQtZCN w==; X-CSE-ConnectionGUID: hV5QNWsDRNeWT6DD4+0r9w== X-CSE-MsgGUID: zyp/cB/OQI6PxkSBENXT7w== X-IronPort-AV: E=McAfee;i="6800,10657,11631"; a="77136566" X-IronPort-AV: E=Sophos;i="6.20,247,1758610800"; d="scan'208";a="77136566" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2025 15:01:44 -0800 X-CSE-ConnectionGUID: iafqWAoBQZGMBBV/tLdIww== X-CSE-MsgGUID: S+YoPmfDSRiUGxMt3Qjmgw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,247,1758610800"; d="scan'208";a="199763904" Received: from b04f130c83f2.jf.intel.com ([10.165.154.98]) by fmviesa004.fm.intel.com with ESMTP; 03 Dec 2025 15:01:43 -0800 From: Tim Chen To: Peter Zijlstra , Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot Cc: Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Tim Chen , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , linux-kernel@vger.kernel.org, Libo Chen Subject: [PATCH v2 16/23] sched/cache: Introduce sched_cache_present to enable cache aware scheduling for multi LLCs NUMA node Date: Wed, 3 Dec 2025 15:07:35 -0800 Message-Id: <7453e3f901878608959f23dacaa36dfc0432c05b.1764801860.git.tim.c.chen@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Yu Cache-aware load balancing should only be enabled if there are more than 1 LLCs within 1 NUMA node. sched_cache_present is introduced to indicate whether this platform supports this topology. Suggested-by: Libo Chen Suggested-by: Adam Li Signed-off-by: Chen Yu Signed-off-by: Tim Chen --- Notes: v1->v2: Use flag sched_cache_present to indicate whether a platform supports cache aware scheduling. Change this flag from staic key. There should be only 1 static key to control the cache aware scheduling. (Peter Zijlstra) kernel/sched/topology.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index d583399fc6a1..9799e3a9a609 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -24,6 +24,8 @@ int max_llcs; =20 #ifdef CONFIG_SCHED_CACHE =20 +static bool sched_cache_present; + static unsigned int *alloc_new_pref_llcs(unsigned int *old, unsigned int *= *gc) { unsigned int *new =3D NULL; @@ -54,7 +56,7 @@ static void populate_new_pref_llcs(unsigned int *old, uns= igned int *new) new[i] =3D old[i]; } =20 -static int resize_llc_pref(void) +static int resize_llc_pref(bool has_multi_llcs) { unsigned int *__percpu *tmp_llc_pref; int i, ret =3D 0; @@ -102,6 +104,11 @@ static int resize_llc_pref(void) rq_unlock_irqrestore(rq, &rf); } =20 + if (has_multi_llcs) { + sched_cache_present =3D true; + pr_info_once("Cache aware load balance is enabled on the platform.\n"); + } + release_old: /* * Load balance is done under rcu_lock. @@ -124,7 +131,7 @@ static int resize_llc_pref(void) =20 #else =20 -static int resize_llc_pref(void) +static int resize_llc_pref(bool has_multi_llcs) { max_llcs =3D new_max_llcs; return 0; @@ -2644,6 +2651,7 @@ static int build_sched_domains(const struct cpumask *cpu_map, struct sched_domain_att= r *attr) { enum s_alloc alloc_state =3D sa_none; + bool has_multi_llcs =3D false; struct sched_domain *sd; struct s_data d; struct rq *rq =3D NULL; @@ -2736,10 +2744,12 @@ build_sched_domains(const struct cpumask *cpu_map, = struct sched_domain_attr *att * between LLCs and memory channels. */ nr_llcs =3D sd->span_weight / child->span_weight; - if (nr_llcs =3D=3D 1) + if (nr_llcs =3D=3D 1) { imb =3D sd->span_weight >> 3; - else + } else { imb =3D nr_llcs; + has_multi_llcs =3D true; + } imb =3D max(1U, imb); sd->imb_numa_nr =3D imb; =20 @@ -2787,7 +2797,7 @@ build_sched_domains(const struct cpumask *cpu_map, st= ruct sched_domain_attr *att if (has_cluster) static_branch_inc_cpuslocked(&sched_cluster_active); =20 - resize_llc_pref(); + resize_llc_pref(has_multi_llcs); =20 if (rq && sched_debug_verbose) pr_info("root domain span: %*pbl\n", cpumask_pr_args(cpu_map)); --=20 2.32.0