From nobody Sun Dec 14 06:18:13 2025 Received: from mta-65-227.siemens.flowmailer.net (mta-65-227.siemens.flowmailer.net [185.136.65.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B06A717D35B for ; Mon, 26 Aug 2024 14:29:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724682551; cv=none; b=hEdw56QsiMGO02KRv17Trq9zwijFU3BerOJRx6xv4BcROG/1fvCSTXIlRQzvDL+pxeJppo4FFB+/B3/0OrrrUPSKopmAvj+l8LCIBcLHwU+3VzbQHrnADfEnY1yeIklFtfnr3KXJnzXwCdZzKqSH8BdkvG3Ol5jr0aECsAbWUzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724682551; c=relaxed/simple; bh=KQDjVGlS1MvzhndxRSElYqb6hfSxS9TDM5jZsjzmMeM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HiBc1mC4bTZrRR1PwKSkkazWN2VLPEpRkuaF7ZBIFZO7xItA/vpkv8TNplw/tgD8556oiT05aW7TnPh+EMeYCJc06eDbMkuOY0RrdqgpFtrQAsudhzySAmAxYPIrOqo09rp9azzp5J1vITHWkMlnGHwvTnsPV2O8RG3/yZdlQDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b=NPSr3PDW; arc=none smtp.client-ip=185.136.65.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b="NPSr3PDW" Received: by mta-65-227.siemens.flowmailer.net with ESMTPSA id 2024082614290297f0fd2bdf9b41c8ba for ; Mon, 26 Aug 2024 16:29:02 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=EVq9VQ8J6EPvFL5j90kLD0YYUlBOESmGhSbO7jhKHWM=; b=NPSr3PDWhUex5gCsrqMDho/T4x1KETj86XQXgeQKwyYn98/3H6MIRl5JRml0pchiapen7L dF1Lef4glvh0h3a9bWcSgYsaAdOItuDuG6E+Ir2cKfiR7Eyylt+vhJgQOicSCklwrQhn8aE4 iWq/2c/4CRqy3kRxXJedn0N4CiHxC0bwax8Q89wjQKTKXbY0zNVUtUm8cwdQLEWtk3FbNWX2 7hIH6JpfIxowTlIcWqcz9ytpmsWR4946pL73Fj8SnNvPW2rNylA9wdhzsE6q8TgHVY79LE4O 4fx1wcxxvWYpSKJfTAbdPBjsFhhwcUcWqFllQkBTvTt5NCH5Gz1tEG9A==; From: Jan Kiszka To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bao Cheng Su , Hua Qian Li Subject: [PATCH 2/2] arm64: dts: ti: iot2050: Add overlays for M.2 used by firmware Date: Mon, 26 Aug 2024 16:28:59 +0200 Message-ID: <7062ec915ecd161f6c62952eb7c1cd5036785dba.1724682539.git.jan.kiszka@siemens.com> In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka To allow firmware to pick up all DTs from here, move the overlays that are normally applied during DT fixup to the kernel source as well. Hook then into the build nevertheless to ensure that regular checks are performed. Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/Makefile | 2 + ...48-iot2050-advanced-m2-bkey-ekey-pcie.dtso | 27 +++++++++++ ...-am6548-iot2050-advanced-m2-bkey-usb3.dtso | 47 +++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bk= ey-ekey-pcie.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bk= ey-usb3.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index e20b27ddf901..f459af7fac0d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -77,6 +77,8 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced-m2.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dt= bo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced-sm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am654-base-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey= -pcie.dtso b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey= -pcie.dtso new file mode 100644 index 000000000000..666237f6d79c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.d= tso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0 + * Copyright (c) Siemens AG, 2022-2024 + * + * Authors: + * Chao Zeng + * Jan Kiszka + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&pcie0_rc { + num-lanes =3D <1>; + phys =3D <&serdes0 PHY_TYPE_PCIE 1>; + phy-names =3D "pcie-phy0"; + reset-gpios =3D <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&pcie1_rc { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3= .dtso b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso new file mode 100644 index 000000000000..0f86235c9771 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0 + * Copyright (c) Siemens AG, 2022-2024 + * + * Authors: + * Chao Zeng + * Jan Kiszka + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&serdes0 { + assigned-clock-parents =3D <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&pcie0_rc { + status =3D "disabled"; +}; + +&pcie1_rc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&minipcie_pins_default>; + + num-lanes =3D <1>; + phys =3D <&serdes1 PHY_TYPE_PCIE 0>; + phy-names =3D "pcie-phy0"; + reset-gpios =3D <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&dwc3_0 { + assigned-clock-parents =3D <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e= . PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys =3D <&serdes0 PHY_TYPE_USB3 0>; + phy-names =3D "usb3-phy"; +}; + +&usb0 { + maximum-speed =3D "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; --=20 2.43.0