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Tue, 16 Dec 2025 20:26:18 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH rc v4 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Date: Tue, 16 Dec 2025 20:26:02 -0800 Message-ID: <6fcdd663d62dcab4005401bac2d23d18dd28e0c4.1765945258.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7C:EE_|IA4PR12MB9764:EE_ X-MS-Office365-Filtering-Correlation-Id: ec2016ce-ec44-425a-4177-08de3d24731b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BjKVYW7v4rkd/sF9+WlZmyZqhw+nUU0WTCqqq0QACkq8qjoxmrL2ezw1hpXb?= =?us-ascii?Q?Sj1Zg5LA69mYbfmPgDNZ9TMOLoR12o220KhFV05dHVMVOKSKbRYBr4qnNLVB?= =?us-ascii?Q?Zfmd3rVRSks8CPeJuabETfX4deKSItDqBVHMeiPVZDgpD6XQDStIqb5Nyn8W?= =?us-ascii?Q?t4QtgpQcgfYhfctdHdAN2Pa8ZiIS2+7CS1uPLBUL3xX5RiMDvCtlAFVgknG2?= =?us-ascii?Q?b2bM4OUfWJ2OIzQSZDoYBWUvlB/m9cIjlcj19z1qAtdEbf5bN+ytyAAg4Bgi?= =?us-ascii?Q?ffEdlugNw4yHV6Amd7Dae7aA5fR0rW726wac3GAOTLwz/KzTIHk2wBlczI4G?= =?us-ascii?Q?yJK2DcrEdz9y8aeQmaXO2sMRpdZuYXbKraCozFTEI0OjK3N6HWtJXyJa3eif?= =?us-ascii?Q?6JngYN4QQEKDM8t1xE4BftS8WaHtYW1On89Q3MakABHX8EfA1y571r51ZzB9?= =?us-ascii?Q?zuu/Q14Zkz8n1PXTAmYjlg1/FvloX11bq1eDvZnT5BIGs9VcTtZVIkRsKCuB?= =?us-ascii?Q?NNCHr3f+ew3Ly/bvD0+Cs/46g3HB3T1rCcHB989D5o3SJ/dPeZOoQqeSddTy?= =?us-ascii?Q?j+nGh6gYO9Gw2ApWdkZ1hnUbtOTzxEE9nJtSidlJEflP74gKiEra9xXXQEUM?= =?us-ascii?Q?sEEpsesFR67SfIUwjTbE7yyHgZE9w1NNiEtt+uAHfjYXs8P3+YXzxKYOCEnj?= =?us-ascii?Q?xWUP891NmqRPYDFvl6PKEoprSdOZW2LDYLVXnBBHHQCCD7Xjs2fJJXmayYyr?= =?us-ascii?Q?q+1aUGMyQJNMyST4ilvkYMlarch+yI68j5yj8GzKqfXciXjR0Eyh6dnhY71I?= =?us-ascii?Q?K9nQlincDgJ9p2TD36x39t2knev+IbvisRHwx2C57xFuev/QmiWX2UsNZYgR?= =?us-ascii?Q?HBSwxDJGjDKtZmA0gDUXdmfaCZq5hXgwfVZ44D1TMyvNCrej5hVxMwaVuVN/?= =?us-ascii?Q?LYoCPYBsUxbcB4AfOsrKhog6IZ4nCSLBQJhp/0BisvvqA5aMMD6wbPqWG2lB?= =?us-ascii?Q?NC3aySnmy37jsQVOAUuolH2+97by7bmSM/Z666XN9guqXyvCGKg2Ft+nfgL5?= =?us-ascii?Q?jTyGHpyB/nzMKiMLveCzGgPERLXjGXp5OyrT/y1310LagyQyBarjbXoaqNc/?= =?us-ascii?Q?AmdjgOfBKst3E9aiHRdP50oU3dvCqWj0qSOhKAuF1qhfwbe13Kh7JJxgcqcE?= =?us-ascii?Q?p/EWmcPZskzwimwv9Xg7IKEcxeChGDDFv90ovkMoOSWxXd9pi9hoLD6PGjrz?= =?us-ascii?Q?OOCY6Wmpxd7rLVxDD4zxWEXL/pYjPdSEY+QRILyWcTRdK53C/LPJHP7GEp1N?= =?us-ascii?Q?wBN6ogJSTarYDeEgBulwp7AJ8mIMzQmNtEJMtqsXNLctV+7rszTECVkj6B/b?= =?us-ascii?Q?Hj5oEfSY8utfk53DjDdCh04V2QVG55tS9GqG4OSwddSOFhAXWd+Y5Umk1ztB?= =?us-ascii?Q?ZzAw4Ufcdd/77W0NSyvU4ptUaFPlOgvsREIycQXe3srSDopMyrCI99H/+gsH?= =?us-ascii?Q?bTFkBGk7x1K/cfNVHW4l7aZ0+SVJtgEqRuaMeg8jK9znJMsIrx6kGay9ZeKe?= =?us-ascii?Q?PrCLS09eqBDuWN7fl8g=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2025 04:26:29.0941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec2016ce-ec44-425a-4177-08de3d24731b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR12MB9764 Content-Type: text/plain; charset="utf-8" STE in a nested case requires both S1 and S2 fields. And this makes the use case different from the existing one. Add coverage for previously failed cases shifting between S2-only and S1+S2 STEs. Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 5db14718fdd6..8255a02f4efa 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -33,8 +33,12 @@ static struct mm_struct sva_mm =3D { enum arm_smmu_test_master_feat { ARM_SMMU_MASTER_TEST_ATS =3D BIT(0), ARM_SMMU_MASTER_TEST_STALL =3D BIT(1), + ARM_SMMU_MASTER_TEST_NESTED =3D BIT(2), }; =20 +static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, + enum arm_smmu_test_master_feat feat); + static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, const __le64 *target, @@ -197,6 +201,17 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_= smmu_ste *ste, }; =20 arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); + if (feat & ARM_SMMU_MASTER_TEST_NESTED) { + struct arm_smmu_ste s2ste; + int i; + + arm_smmu_test_make_s2_ste(&s2ste, ARM_SMMU_MASTER_TEST_ATS); + ste->data[0] |=3D cpu_to_le64( + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); + ste->data[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); + for (i =3D 2; i < NUM_ENTRY_QWORDS; i++) + ste->data[i] =3D s2ste.data[i]; + } } =20 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) @@ -554,6 +569,35 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(= struct kunit *test) NUM_EXPECTED_SYNCS(3)); } =20 +static void +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + /* Expect an additional sync to unset ignored bits: EATS and MEV */ + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(2)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -600,6 +644,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.43.0