From nobody Tue Apr 7 10:41:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 214FA2DAFA9; Sat, 4 Apr 2026 01:56:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775267810; cv=none; b=nazCFl+Q6gUHxAgfssHuogIhPcfon1Hu9i5DAt/FkF1uPI/V6N3XLSikOgqQgcMKOH4Za/oaE2pzZeZsDrteLue1Dnqt2AVJBbRIJRLYgz+x6DXc1xKUnoHCfY1naynT+o2QYUFDpCQuLh35BP18PjdcAz2hLE6TfL3aVQQvCfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775267810; c=relaxed/simple; bh=lUjxt+hDZL+o4Rrc+j7qS62qkbC6Cn6HcahwNmT9Z3w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z1P+jVIsfAZtnA3Jcq/n6VpBdxDdHVxpT3LUpU0bD+ypVU3Ag26KcGwhNQxJDPGcewDvJ+nthI3WezZ2uGfcKsdphhXq4EEPwxcDQRNkFndgEwuR/6hP/5aJh3xMqbKbsyKEIQAAsMdXrwpg20D2MF0Ex3/emi4QpBBrnVnJnng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hXvc50JZ; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hXvc50JZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775267809; x=1806803809; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lUjxt+hDZL+o4Rrc+j7qS62qkbC6Cn6HcahwNmT9Z3w=; b=hXvc50JZNCMbY5Xyb1YKIoILgeplX+LxxE5VxPYxQxpooeTkGFGnjVRr G5jTHU3rs3knmcidqsrazsxFUygU7+XCWZEylPvqsyOB6sg0uptYHsyUS iLHCrV++22dVndlmlmJvUIk52Cp3LBW+h8YuyCETMMw0d1OHMbqWUE0OX 83CFNqpL8rENBkN/9SFCPWtn72buMW8MuQf65z8SNsaeFzfy56RK3vqhm v6m+bixvG7tFLfUkkzPPUsB29M9BEn+dY4D3O4nuKZ2FEpegVwog+hLri CR0gkkP3xvfY3LniBaTyVwoYRhniYSpKCXB+OsBNdBFlIxE4268d5IQgo g==; X-CSE-ConnectionGUID: ykdn9ujMQK6msyVSk93f2w== X-CSE-MsgGUID: 6eZ28w3mRpKpb/TL36C/4A== X-IronPort-AV: E=McAfee;i="6800,10657,11748"; a="76343415" X-IronPort-AV: E=Sophos;i="6.23,158,1770624000"; d="scan'208";a="76343415" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2026 18:56:45 -0700 X-CSE-ConnectionGUID: sSONFkpRQCSZL3lICQq0Ug== X-CSE-MsgGUID: t6bm+Mq/SuSvCph+5c1JIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,158,1770624000"; d="scan'208";a="224121548" Received: from rchatre-desk1.jf.intel.com ([10.165.154.99]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2026 18:56:19 -0700 From: Reinette Chatre To: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, tony.luck@intel.com, babu.moger@amd.com, ilpo.jarvinen@linux.intel.com Cc: fenghuay@nvidia.com, peternewman@google.com, zide.chen@intel.com, dapeng1.mi@linux.intel.com, ben.horgan@arm.com, yu.c.chen@intel.com, jason.zeng@intel.com, reinette.chatre@intel.com, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v4 08/10] selftests/resctrl: Remove requirement on cache miss rate Date: Fri, 3 Apr 2026 18:56:07 -0700 Message-ID: <6de4da5486354c0f25fef0d194956470cb744041.1775266384.git.reinette.chatre@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable As the CAT test reads the same buffer into different sized cache portions it compares the number of cache misses against an expected percentage based on the size of the cache portion. Systems and test conditions vary. The CAT test is a test of resctrl subsystem health and not a test of the hardware architecture so it is not required to place requirements on the size of the difference in cache misses, just that the number of cache misses when reading a buffer increase as the cache portion used for the buffer decreases. Remove additional constraint on how big the difference between cache misses should be as the cache portion size changes. Only test that the cache misses increase as the cache portion size decreases. This remains a good sanity check of resctrl subsystem health while reducing impact of hardware architectural differences and the various conditions under which the test may run. Increase the size difference between cache portions to additionally avoid any consequences resulting from smaller increments. Signed-off-by: Reinette Chatre Tested-by: Chen Yu Reviewed-by: Ilpo J=C3=A4rvinen --- Changes since v2: - Add Chen Yu's tag. Changes since v3: - Add Ilpo's RB tag. --- tools/testing/selftests/resctrl/cat_test.c | 33 ++++------------------ 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index f00b622c1460..8bc47f06679a 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -14,42 +14,20 @@ #define RESULT_FILE_NAME "result_cat" #define NUM_OF_RUNS 5 =20 -/* - * Minimum difference in LLC misses between a test with n+1 bits CBM to the - * test with n bits is MIN_DIFF_PERCENT_PER_BIT * (n - 1). With e.g. 5 vs 4 - * bits in the CBM mask, the minimum difference must be at least - * MIN_DIFF_PERCENT_PER_BIT * (4 - 1) =3D 3 percent. - * - * The relationship between number of used CBM bits and difference in LLC - * misses is not expected to be linear. With a small number of bits, the - * margin is smaller than with larger number of bits. For selftest purpose= s, - * however, linear approach is enough because ultimately only pass/fail - * decision has to be made and distinction between strong and stronger - * signal is irrelevant. - */ -#define MIN_DIFF_PERCENT_PER_BIT 1UL - static int show_results_info(__u64 sum_llc_val, int no_of_bits, unsigned long cache_span, - unsigned long min_diff_percent, unsigned long num_of_runs, bool platform, __s64 *prev_avg_llc_val) { __u64 avg_llc_val =3D 0; - float avg_diff; int ret =3D 0; =20 avg_llc_val =3D sum_llc_val / num_of_runs; if (*prev_avg_llc_val) { - float delta =3D (__s64)(avg_llc_val - *prev_avg_llc_val); - - avg_diff =3D delta / *prev_avg_llc_val; - ret =3D platform && (avg_diff * 100) < (float)min_diff_percent; - - ksft_print_msg("%s Check cache miss rate changed more than %.1f%%\n", - ret ? "Fail:" : "Pass:", (float)min_diff_percent); + ret =3D platform && (avg_llc_val < *prev_avg_llc_val); =20 - ksft_print_msg("Percent diff=3D%.1f\n", avg_diff * 100); + ksft_print_msg("%s Check cache miss rate increased\n", + ret ? "Fail:" : "Pass:"); } *prev_avg_llc_val =3D avg_llc_val; =20 @@ -58,10 +36,10 @@ static int show_results_info(__u64 sum_llc_val, int no_= of_bits, return ret; } =20 -/* Remove the highest bit from CBM */ +/* Remove the highest bits from CBM */ static unsigned long next_mask(unsigned long current_mask) { - return current_mask & (current_mask >> 1); + return current_mask & (current_mask >> 2); } =20 static int check_results(struct resctrl_val_param *param, const char *cach= e_type, @@ -112,7 +90,6 @@ static int check_results(struct resctrl_val_param *param= , const char *cache_type =20 ret =3D show_results_info(sum_llc_perf_miss, bits, alloc_size / 64, - MIN_DIFF_PERCENT_PER_BIT * (bits - 1), runs, get_vendor() =3D=3D ARCH_INTEL, &prev_avg_llc_val); if (ret) --=20 2.50.1