From nobody Wed Sep 30 15:28:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AB3443E4A2 for ; Fri, 7 Aug 2026 05:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786080974; cv=none; b=GUk8Jlkl0E+Yni3tuvtwGgwtcRAXbW8hF+b2gIViTNYiZeTTfoJCQJvnXWLRgqN/V9PouCUn+sSRrK7hM70AHgCdwq43b9r005H18HXq1BhRyRcuSEc9mTw6LaHyhepkj1UpvATDm5o59rXuBIHG37vSAmtWvwBycG8JcxTJ9Ag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786080974; c=relaxed/simple; bh=1woWX/X91UmwPsG4AqjMQzLoWo4AhbpQz9HxDwH39vY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=jdFQWbdVaPZrNMTLp+QHr4QVJRbTKI1nFgg18fEbnvOf6RBHWFh8+tx05FAtyicckZiuBG5j4TmczQH0bLJPGhvnFBvUpsl3EdINfK3xuvXe+0eAf/moa9iZoE8IEm5zDg2hyo1FvUvdzY48h+mtnaK/i2QbN88xL5tbWlhPbeA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JulXg+KG; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JulXg+KG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CDAA1F000E9; Fri, 7 Aug 2026 05:36:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786080971; bh=kNkdOQcC2ETToC90VfwFI80Jg9M/yh183B14tDW5Vmo=; h=From:To:Cc:Subject:Date; b=JulXg+KG1FRQKQrSmKoNSJIVYeGcDT4ofxR3TE1zp5uJhq56kCSz2Q4PgWpKwnOsk /fpRwRBOlBl5AYNUltHWiAOP/HE7TZGoA39d9s0OTUd6FhoN2iVEz2Ei0a6qdv2oU0 /ec5i0k2TGlxOvvefy/5lMMpqy6hrdhdgOYW7E9JVsY7pYV4IlW6FQqYug2cOYitsb g+yA8Ucvlu4lHIWhxx5SVOeWB24xcOPH6vTdse80e8jFUCkPEeCq6zK7fOYBi0Ukot wKHxlcdLh4H+fVXHoqYETlY73apRDs00z9cu1oicMRSx+ZHmrW4PZLd04Vizopev/h VB3T3xOraMOTA== From: "Christophe Leroy (CS GROUP)" To: Qiang Zhao , "Christophe Leroy (CS GROUP)" Cc: linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel test robot Subject: [PATCH] soc: fsl: qe: Fix sparse warnings in GPIO Date: Fri, 7 Aug 2026 07:35:52 +0200 Message-ID: <6a84b38e766729676b375c93bf54c67ea455288d.1786080840.git.chleroy@kernel.org> X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5703; i=chleroy@kernel.org; h=from:subject:message-id; bh=1woWX/X91UmwPsG4AqjMQzLoWo4AhbpQz9HxDwH39vY=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWSV5u1SfhATN3ultMOUTYX/96r+crp2+PbEGca1/k3Sd 1amlReJdZSyMIhxMciKKbIc/8+9a0bXl9T8qbv0YeawMoEMYeDiFICJbLNkZNhmsGmaostPwYxt J1Ysf+naG+zPde0Rq8jetUYfzasmnBFm+MO13Ly/JVfq5F3PG4/7LJ0c7xh+SxIVltuYpnbxsNE KIyYA X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A C=3D2 build on mpc83xx_defconfig provides following warnings: drivers/soc/fsl/qe/gpio.c:44:34: warning: incorrect type in assignment (d= ifferent base types) drivers/soc/fsl/qe/gpio.c:44:34: expected restricted __be32 [usertype]= cpdata drivers/soc/fsl/qe/gpio.c:44:34: got unsigned int [usertype] cpdata drivers/soc/fsl/qe/gpio.c:45:34: warning: incorrect type in assignment (d= ifferent base types) drivers/soc/fsl/qe/gpio.c:45:34: expected restricted __be32 [usertype]= cpdir1 drivers/soc/fsl/qe/gpio.c:45:34: got unsigned int drivers/soc/fsl/qe/gpio.c:46:34: warning: incorrect type in assignment (d= ifferent base types) drivers/soc/fsl/qe/gpio.c:46:34: expected restricted __be32 [usertype]= cpdir2 drivers/soc/fsl/qe/gpio.c:46:34: got unsigned int drivers/soc/fsl/qe/gpio.c:47:34: warning: incorrect type in assignment (d= ifferent base types) drivers/soc/fsl/qe/gpio.c:47:34: expected restricted __be32 [usertype]= cppar1 drivers/soc/fsl/qe/gpio.c:47:34: got unsigned int drivers/soc/fsl/qe/gpio.c:48:34: warning: incorrect type in assignment (d= ifferent base types) drivers/soc/fsl/qe/gpio.c:48:34: expected restricted __be32 [usertype]= cppar2 drivers/soc/fsl/qe/gpio.c:48:34: got unsigned int drivers/soc/fsl/qe/gpio.c:49:33: warning: incorrect type in assignment (d= ifferent base types) drivers/soc/fsl/qe/gpio.c:49:33: expected restricted __be32 [usertype]= cpodr drivers/soc/fsl/qe/gpio.c:49:33: got unsigned int drivers/soc/fsl/qe/gpio.c:297:17: warning: restricted __be32 degrades to = integer drivers/soc/fsl/qe/gpio.c:299:17: warning: restricted __be32 degrades to = integer drivers/soc/fsl/qe/gpio.c:302:17: warning: restricted __be32 degrades to = integer drivers/soc/fsl/qe/gpio.c:304:17: warning: restricted __be32 degrades to = integer drivers/soc/fsl/qe/gpio.c:308:18: warning: restricted __be32 degrades to = integer drivers/soc/fsl/qe/gpio.c:314:9: warning: restricted __be32 degrades to i= nteger The problem is the 'struct qe_pio_reg' embedded in 'struct qe_gpio_chip' to save register values. As the values are read with ioread32be(), they are now in CPU byte order and can't be stored as-is in a __be32 object. Replace 'struct qe_pio_reg saved_regs' by individual u32 fields. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202608051952.ADkLIB86-lkp@int= el.com/ Signed-off-by: Christophe Leroy (CS GROUP) --- drivers/soc/fsl/qe/gpio.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 5cd59cfbf22f..8e210f8a3b6c 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -32,8 +32,13 @@ struct qe_gpio_chip { /* shadowed data register to clear/set bits safely */ u32 cpdata; =20 - /* saved_regs used to restore dedicated functions */ - struct qe_pio_regs saved_regs; + /* saved regs used to restore dedicated functions */ + u32 saved_cpodr; + u32 saved_cpdata; + u32 saved_cpdir1; + u32 saved_cpdir2; + u32 saved_cppar1; + u32 saved_cppar2; }; =20 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) @@ -41,12 +46,12 @@ static void qe_gpio_save_regs(struct qe_gpio_chip *qe_g= c) struct qe_pio_regs __iomem *regs =3D qe_gc->regs; =20 qe_gc->cpdata =3D ioread32be(®s->cpdata); - qe_gc->saved_regs.cpdata =3D qe_gc->cpdata; - qe_gc->saved_regs.cpdir1 =3D ioread32be(®s->cpdir1); - qe_gc->saved_regs.cpdir2 =3D ioread32be(®s->cpdir2); - qe_gc->saved_regs.cppar1 =3D ioread32be(®s->cppar1); - qe_gc->saved_regs.cppar2 =3D ioread32be(®s->cppar2); - qe_gc->saved_regs.cpodr =3D ioread32be(®s->cpodr); + qe_gc->saved_cpdata =3D qe_gc->cpdata; + qe_gc->saved_cpdir1 =3D ioread32be(®s->cpdir1); + qe_gc->saved_cpdir2 =3D ioread32be(®s->cpdir2); + qe_gc->saved_cppar1 =3D ioread32be(®s->cppar1); + qe_gc->saved_cppar2 =3D ioread32be(®s->cppar2); + qe_gc->saved_cpodr =3D ioread32be(®s->cpodr); } =20 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) @@ -284,7 +289,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) { struct qe_gpio_chip *qe_gc =3D qe_pin->controller; struct qe_pio_regs __iomem *regs =3D qe_gc->regs; - struct qe_pio_regs *sregs =3D &qe_gc->saved_regs; int pin =3D qe_pin->num; u32 mask1 =3D 1 << (QE_PIO_PINS - (pin + 1)); u32 mask2 =3D 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); @@ -294,24 +298,20 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) spin_lock_irqsave(&qe_gc->lock, flags); =20 if (second_reg) { - qe_clrsetbits_be32(®s->cpdir2, mask2, - sregs->cpdir2 & mask2); - qe_clrsetbits_be32(®s->cppar2, mask2, - sregs->cppar2 & mask2); + qe_clrsetbits_be32(®s->cpdir2, mask2, qe_gc->saved_cpdir2 & mask2); + qe_clrsetbits_be32(®s->cppar2, mask2, qe_gc->saved_cppar2 & mask2); } else { - qe_clrsetbits_be32(®s->cpdir1, mask2, - sregs->cpdir1 & mask2); - qe_clrsetbits_be32(®s->cppar1, mask2, - sregs->cppar1 & mask2); + qe_clrsetbits_be32(®s->cpdir1, mask2, qe_gc->saved_cpdir1 & mask2); + qe_clrsetbits_be32(®s->cppar1, mask2, qe_gc->saved_cppar1 & mask2); } =20 - if (sregs->cpdata & mask1) + if (qe_gc->saved_cpdata & mask1) qe_gc->cpdata |=3D mask1; else qe_gc->cpdata &=3D ~mask1; =20 iowrite32be(qe_gc->cpdata, ®s->cpdata); - qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); + qe_clrsetbits_be32(®s->cpodr, mask1, qe_gc->saved_cpodr & mask1); spin_unlock_irqrestore(&qe_gc->lock, flags); } EXPORT_SYMBOL(qe_pin_set_dedicated); --=20 2.54.0