From nobody Tue Apr 7 14:41:20 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD78734D4F5; Fri, 13 Mar 2026 06:09:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773382158; cv=none; b=P2iLfN5N2tANiuUzC14y0C3kbARmQls1vRgpc1y0MpZUDCuuuVDLfOLG78tX6AbikGwpFFMOYJPvcq8UbIbOk8PGDLsl9hAGkhoQovVHXKTEWI8mjm/01AEwGTH88/cgxpkdocbl8Vbd66FRyyH3Ss/U0siKZILlGkOQ3zSYhio= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773382158; c=relaxed/simple; bh=4ZfcPFPmwj9wKHiRm5M5YahNf/Uq/EKO9Ai3geWy5YQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OQ2z+CBEUS+MZNFFfU98UqOkHzJDCcWfHf1GE8pPIpSR0Ody4oFk5nnjLgptQw8ZIw4Xgu6+vl5vBM0mRfMXKb4bqS6kryWUj7JL3NgMmYAs3VheOu1AA6QU6YqiRR6qfqVlIb3WWUIqBpllltkz0MmeKMV3WcIQ4+4gh0CtkM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: 236816c21ea311f1a21c59e7364eecb8-20260313 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:774ba76c-ff1f-4aa0-9545-ff8c73c52fd4,IP:0,U RL:0,TC:0,Content:-25,EDM:25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:89c9d04,CLOUDID:a252da3c25ab9bafebde4d8575e874d7,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|850|898,TC:nil,Content:0|15|50 ,EDM:5,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OS A:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 236816c21ea311f1a21c59e7364eecb8-20260313 X-User: xiaopei01@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 68105137; Fri, 13 Mar 2026 14:09:04 +0800 From: Pei Xiao To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, openbmc@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Cc: Pei Xiao Subject: [PATCH v2 16/17] spi: zynq-qspi: Use helper function devm_clk_get_enabled() Date: Fri, 13 Mar 2026 14:08:32 +0800 Message-Id: <69a54f7c4d839c9033b1bd088eecf505ef810493.1773381582.git.xiaopei01@kylinos.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables the clocks. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Simplify code. Signed-off-by: Pei Xiao --- drivers/spi/spi-zynq-qspi.c | 28 ++++++---------------------- 1 file changed, 6 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index 5232483c4a3a..f887c55337ae 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -661,7 +661,7 @@ static int zynq_qspi_probe(struct platform_device *pdev) goto remove_ctlr; } =20 - xqspi->pclk =3D devm_clk_get(&pdev->dev, "pclk"); + xqspi->pclk =3D devm_clk_get_enabled(&pdev->dev, "pclk"); if (IS_ERR(xqspi->pclk)) { dev_err(&pdev->dev, "pclk clock not found.\n"); ret =3D PTR_ERR(xqspi->pclk); @@ -670,36 +670,24 @@ static int zynq_qspi_probe(struct platform_device *pd= ev) =20 init_completion(&xqspi->data_completion); =20 - xqspi->refclk =3D devm_clk_get(&pdev->dev, "ref_clk"); + xqspi->refclk =3D devm_clk_get_enabled(&pdev->dev, "ref_clk"); if (IS_ERR(xqspi->refclk)) { dev_err(&pdev->dev, "ref_clk clock not found.\n"); ret =3D PTR_ERR(xqspi->refclk); goto remove_ctlr; } =20 - ret =3D clk_prepare_enable(xqspi->pclk); - if (ret) { - dev_err(&pdev->dev, "Unable to enable APB clock.\n"); - goto remove_ctlr; - } - - ret =3D clk_prepare_enable(xqspi->refclk); - if (ret) { - dev_err(&pdev->dev, "Unable to enable device clock.\n"); - goto clk_dis_pclk; - } - xqspi->irq =3D platform_get_irq(pdev, 0); if (xqspi->irq < 0) { ret =3D xqspi->irq; - goto clk_dis_all; + goto remove_ctlr; } ret =3D devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, 0, pdev->name, xqspi); if (ret !=3D 0) { ret =3D -ENXIO; dev_err(&pdev->dev, "request_irq failed\n"); - goto clk_dis_all; + goto remove_ctlr; } =20 ret =3D of_property_read_u32(np, "num-cs", @@ -709,7 +697,7 @@ static int zynq_qspi_probe(struct platform_device *pdev) } else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) { ret =3D -EINVAL; dev_err(&pdev->dev, "only 2 chip selects are available\n"); - goto clk_dis_all; + goto remove_ctlr; } else { ctlr->num_chipselect =3D num_cs; } @@ -728,15 +716,11 @@ static int zynq_qspi_probe(struct platform_device *pd= ev) ret =3D devm_spi_register_controller(&pdev->dev, ctlr); if (ret) { dev_err(&pdev->dev, "devm_spi_register_controller failed\n"); - goto clk_dis_all; + goto remove_ctlr; } =20 return ret; =20 -clk_dis_all: - clk_disable_unprepare(xqspi->refclk); -clk_dis_pclk: - clk_disable_unprepare(xqspi->pclk); remove_ctlr: spi_controller_put(ctlr); =20 --=20 2.25.1