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Fri, 3 Jan 2025 11:44:32 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 14/14] iommu/arm-smmu-v3: Report events that belong to devices attached to vIOMMU Date: Fri, 3 Jan 2025 11:43:37 -0800 Message-ID: <69a46c72e43ed086840be462eef731167d90a9d8.1735933254.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06E:EE_|SN7PR12MB8059:EE_ X-MS-Office365-Filtering-Correlation-Id: c9d7d69b-1786-4f0a-d4b8-08dd2c2f1716 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?7S1o1ic8wlyjoo9st7m6Qxc4C85sKk6u104buP3bsMQR36Dk7eT0jP1XsQwY?= =?us-ascii?Q?B8HDUk95mJtQDF4jJ/5D2GyuvIVDxoLwWt1xGnt4UM6P7sctdmOnDDztfj8W?= =?us-ascii?Q?oOLVG1DiMrVQo4Vag3DJEwMXx6klfJ/rZBghB6IOxAT54Kqc8GOBFQd6VhFz?= =?us-ascii?Q?7MMHW4O7igOBPbt2ab9m7ONq474wCGbqZNdZH0y0vn3XXlDv3slmUZ6M7vjw?= =?us-ascii?Q?baowRd9jdpckibVtr+8uTLUHxZPVFY32rSzzIPrEZWEEbwLoxnOaPrVt6ylu?= =?us-ascii?Q?I01Zm9h+zgW7JHgWcWOijJwWfijK486hU+thz23x2xQabRGKr/6JFhpszBJs?= =?us-ascii?Q?wYwMZ3goQu0LEJywoCx8g7nG/1An4SfkhsdO5UxGC1eiuXw2oBhIW5UWHw+S?= =?us-ascii?Q?pwJSS7JOkOu3x97Lgqp644Skj0dDyOQYMLzp84rIsZNEWm/4pY8O178wQ4+u?= =?us-ascii?Q?LjcowSbB4Pafpcc3NxEJjyPk0DArebdFeHVgIWVJdjpuiDSJmylFXmAqZNmO?= =?us-ascii?Q?WyaiaxNNmGLjQrn8M1gnjZZNOvb31LgxLSr+WTrHuQzCQ2Rw9NtJPV4xACkq?= =?us-ascii?Q?78LOIY7XYVMZXH5DS/oFonoT5eUpsu+g67L77TVV0tXXsiZ4G4SqLbTArnIz?= =?us-ascii?Q?vYtuHsk0Gavr+yT1GAkXb21l3RZ+65jXxAQ896e+hU3QGzXnn8rrjYlE7lRc?= =?us-ascii?Q?W8qbCbtqZChIQnyatb/rCxT3Mh8y3kf66P7DFDNnulMV+MiVyoDuzcDtAa7m?= =?us-ascii?Q?Is0a2qf0fLO+5xOmn4icD1AXB8G1yY8z30SKdvn5s0m4QHG3rUUusdj56XR7?= =?us-ascii?Q?JGKnvZjM5y8oB16wDQ+xFMU6wn98mJvLtwB6LU1jqreV4cqe/yBk/sThZYZ5?= =?us-ascii?Q?9n9/8dskyzQsnM7yoW9K5Gl0sIZwNzF/XuMOkIwyIAdac+FrMqPuOWOo7jkG?= =?us-ascii?Q?Lc5dit7mWZMDcu0IHzjrA+lqSqrEOzQH/PjeHD9jRgp/8YvPLH1a2u4JawWs?= =?us-ascii?Q?JlVEFH+oiyoxifOLWvOOirbBeqmy1qTRtV/4Dh8gzy0Y3VLJ7A2s7sSAzOXp?= =?us-ascii?Q?4qLlE0JB2083jE6ox/c0ajmv/CASvo96Y4VUpTQBHCLV+uN3SalAX/U9j44F?= =?us-ascii?Q?NwS8hI5IuYOQab13S3O3nb0Trh6CKPgD6RqFGG8eXdZOwy/ERmACM/WJeGWY?= =?us-ascii?Q?LpUroJmhuJ9CDXnVT1Y8XquZE1FXVyZ28mjd3yo32Ced3+ZLI+vWHwQdYkAo?= =?us-ascii?Q?JV1jr+hSuBWnteNzZmT/DxYtPvZS2R+GdKgyWlz+Ro/KjicYiSSEtQnz4z8b?= =?us-ascii?Q?Z96V2VO3didP5z6If9wfnUTl00aRLUA2xT/ysp+i0+GFTR0CVxHLbN3R138g?= =?us-ascii?Q?8tLMfn61aVc4RTburHhUFKPLYucsCnaCEnXE9cLXcTe1MsBwuK/nrSHN57Fr?= =?us-ascii?Q?tSHT4sjG4mV38L4eUMKBDWAozkhkh+Qk+N17R+3MbfWyxA5rKL5EEQITK+Mx?= =?us-ascii?Q?bCDJsD4VRgZHS9U=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2025 19:44:51.6904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9d7d69b-1786-4f0a-d4b8-08dd2c2f1716 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06E.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8059 Content-Type: text/plain; charset="utf-8" Aside from the IOPF framework, iommufd provides an additional pathway to report hardware events, via the vEVENTQ of vIOMMU infrastructure. Define an iommu_vevent_arm_smmuv3 uAPI structure, and report stage-1 events in the threaded IRQ handler. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +++ include/uapi/linux/iommufd.h | 15 +++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 16 +++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 58 +++++++++++-------- 4 files changed, 71 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 4435ad7db776..d24c3d8ee397 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1066,6 +1066,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device = *dev, int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, struct iommu_domain *domain); void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); +int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); #else #define arm_smmu_hw_info NULL #define arm_vsmmu_alloc NULL @@ -1081,6 +1082,12 @@ static inline void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state) { } + +static inline int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaste= r, + u64 *evt) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */ =20 #endif /* _ARM_SMMU_V3_H */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 0a08aa82e7cc..55e3d5a14cca 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1016,9 +1016,24 @@ struct iommu_ioas_change_process { /** * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use + * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT =3D 0, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 =3D 1, +}; + +/** + * struct iommu_vevent_arm_smmuv3 - ARM SMMUv3 Virtual Event + * (IOMMU_VEVENTQ_TYPE_ARM_SMMUV3) + * @evt: 256-bit ARM SMMUv3 Event record, little-endian. + * (Refer to "7.3 Event records" in SMMUv3 HW Spec) + * + * StreamID field reports a virtual device ID. To receive a virtual event = for a + * device, a vDEVICE must be allocated via IOMMU_VDEVICE_ALLOC. + */ +struct iommu_vevent_arm_smmuv3 { + __aligned_le64 evt[4]; }; =20 /** diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 2b6253ef0e8f..f88fd2f5cae8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -447,4 +447,20 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *= dev, return &vsmmu->core; } =20 +int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt) +{ + struct iommu_vevent_arm_smmuv3 vevt =3D + *(struct iommu_vevent_arm_smmuv3 *)evt; + + vevt.evt[0] &=3D ~EVTQ_0_SID; + vevt.evt[0] |=3D FIELD_PREP(EVTQ_0_SID, vmaster->vsid); + + vevt.evt[0] =3D cpu_to_le64(vevt.evt[0]); + vevt.evt[1] =3D cpu_to_le64(vevt.evt[1]); + + return iommufd_viommu_report_event(&vmaster->vsmmu->core, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, &vevt, + sizeof(vevt)); +} + MODULE_IMPORT_NS("IOMMUFD"); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 686c171dd273..59fbc342a095 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1812,8 +1812,8 @@ static void arm_smmu_decode_event(struct arm_smmu_dev= ice *smmu, u64 *raw, mutex_unlock(&smmu->streams_mutex); } =20 -static int arm_smmu_handle_event(struct arm_smmu_device *smmu, - struct arm_smmu_event *event) +static int arm_smmu_handle_event(struct arm_smmu_device *smmu, u64 *evt, + struct arm_smmu_event *event) { int ret =3D 0; u32 perm =3D 0; @@ -1831,31 +1831,30 @@ static int arm_smmu_handle_event(struct arm_smmu_de= vice *smmu, return -EOPNOTSUPP; } =20 - if (!event->stall) - return -EOPNOTSUPP; - - if (event->read) - perm |=3D IOMMU_FAULT_PERM_READ; - else - perm |=3D IOMMU_FAULT_PERM_WRITE; + if (event->stall) { + if (event->read) + perm |=3D IOMMU_FAULT_PERM_READ; + else + perm |=3D IOMMU_FAULT_PERM_WRITE; =20 - if (event->instruction) - perm |=3D IOMMU_FAULT_PERM_EXEC; + if (event->instruction) + perm |=3D IOMMU_FAULT_PERM_EXEC; =20 - if (event->privileged) - perm |=3D IOMMU_FAULT_PERM_PRIV; + if (event->privileged) + perm |=3D IOMMU_FAULT_PERM_PRIV; =20 - flt->type =3D IOMMU_FAULT_PAGE_REQ; - flt->prm =3D (struct iommu_fault_page_request) { - .flags =3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE, - .grpid =3D event->stag, - .perm =3D perm, - .addr =3D event->iova, - }; + flt->type =3D IOMMU_FAULT_PAGE_REQ; + flt->prm =3D (struct iommu_fault_page_request){ + .flags =3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE, + .grpid =3D event->stag, + .perm =3D perm, + .addr =3D event->iova, + }; =20 - if (event->ssv) { - flt->prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; - flt->prm.pasid =3D event->ssid; + if (event->ssv) { + flt->prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + flt->prm.pasid =3D event->ssid; + } } =20 mutex_lock(&smmu->streams_mutex); @@ -1865,7 +1864,16 @@ static int arm_smmu_handle_event(struct arm_smmu_dev= ice *smmu, goto out_unlock; } =20 - ret =3D iommu_report_device_fault(master->dev, &fault_evt); + if (event->stall) { + ret =3D iommu_report_device_fault(master->dev, &fault_evt); + } else { + down_read(&master->vmaster_rwsem); + if (master->vmaster && !event->s2) + ret =3D arm_vmaster_report_event(master->vmaster, evt); + else + ret =3D -EFAULT; /* Unhandled events should be pinned */ + up_read(&master->vmaster_rwsem); + } out_unlock: mutex_unlock(&smmu->streams_mutex); return ret; @@ -1943,7 +1951,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void= *dev) do { while (!queue_remove_raw(q, evt)) { arm_smmu_decode_event(smmu, evt, &event); - if (arm_smmu_handle_event(smmu, &event)) + if (arm_smmu_handle_event(smmu, evt, &event)) arm_smmu_dump_event(smmu, evt, &event, &rs); =20 put_device(event.dev); --=20 2.43.0