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Tue, 17 Mar 2026 00:59:31 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v13 2/8] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Date: Tue, 17 Mar 2026 00:59:17 -0700 Message-ID: <691686424f35e47bf1ff3f8adbcc0639341c327c.1773733797.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE7:EE_|BY5PR12MB4036:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d35ec99-3df7-40af-dc12-08de83fb2836 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: fkElzNkrLBK18uhySNuUaS5hJbHRKy0CjAXNweU5iJ9k8m7YR4gGTNkstxI8SWmWbsoT86B6Qee9QHmTWAJ/NxHY8iSXKdmd8fBOLYWeWWQPpaup9C+iAJqStDLt7gv1rPdYVoU8JA4+e3NKpRbT6tp2LLMRhRRBaVxyBGxDWx2HEYvsWylB9wxHzon7NbqTsFbQ4YLBmcou3rHOMqJLrOpHQSBi8OMCKFznAzXbzlNhbzsDMYGvSCn40omOIzn8DQdkPWP1Vli+GRa2j/LFjLw+V+u9WYZth5w+Y812GjjvOwydkWVQzQKzuYTQJlv6bnMJ29LKDgUzcwvaylHkW1dxDm0W4jFvX8hpxUDdPzZiUv9DwuB8a842RhYjdUsiIKHg2zbNzGUkfjJHG8F306447ZA31GF4lS+Pi2IavcHjgq0cU55VhFCSb8xVR4EFU4qxlcfCKIWHd2SFLT1NcKuoWvJSzL+Cw9F5UqI9K2Q0fnwF2RFNyrHO/p2YmVNKht530OHZFd+YXN8GTKe5Z9W6wlVcQGZwmfKTb5zZ0hSeSoU+BSme+sNzJbVaEPl0gRPriBsYxQJ9pmOEBKjcObvb1peawXH9NTEA6/lfMTN8y1fjsa5Ri8kasENSRA8GUdrtX0bPsHRurVxGYDY3L+35Z/rEr8GEE2nNDRzw/oYnANXNvy5b3Vrt0OcsN0lhRYQ+py3VyGKce3N6efNCFAcyw61mrgWQDvvM0wJJvZmrsKuRWXHjJM/9T/jchn67JnaqSOchNmJoiSC4WjubvA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700016)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; 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charset="utf-8" Both the ARM_SMMU_DOMAIN_S1 case and the SVA case use ASID, requiring ASID based invalidation commands to flush the TLB. Define an ARM_SMMU_DOMAIN_SVA to make the SVA case clear to share the same path with the ARM_SMMU_DOMAIN_S1 case, which will be a part of the routine to build a new per-domain invalidation array. There is no function change. Suggested-by: Jason Gunthorpe Acked-by: Balbir Singh Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 3c6d65d36164f..24894b1630045 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -856,6 +856,7 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 =3D 0, ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_SVA, }; =20 struct arm_smmu_domain { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80f..6097f1f540d87 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -346,6 +346,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, * ARM_SMMU_FEAT_RANGE_INV is present */ smmu_domain->domain.pgsize_bitmap =3D PAGE_SIZE; + smmu_domain->stage =3D ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu =3D smmu; =20 ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 606abe051e68b..117979c96b762 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3132,6 +3132,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); break; + default: + WARN_ON(true); + break; } =20 arm_smmu_attach_commit(&state); --=20 2.43.0