From nobody Sun Apr 5 13:07:33 2026 Received: from mail-10630.protonmail.ch (mail-10630.protonmail.ch [79.135.106.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18F9A342177 for ; Fri, 20 Feb 2026 12:49:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.30 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771591751; cv=none; b=HumkPBwg/+mjN0ZDIcEJswD3RHBRXPfBYAnCZp3OHRx5YNYas+Pimv3KwUjnVaf7JAethFEcNjwYQaCU6Mq6SiAdCqyzf03w8RLW2tfFd6lOnmElUbo51oQwIzabSl1TYgqT1gLqNYdKuljSgZvUWrQ3iTxLq026MSMQ7ZOMGcg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771591751; c=relaxed/simple; bh=x37Sa9GPIE2tjSJdbrBtSV6yIAv4vCPJZKLIoewTLdM=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IEAIuIJfjbbC+FS7XV92P4Gv9JQ+rk370EQLTYBv/+YsEa0qW5uMYmRuX3nPDk5tbL6pyV/TCIonAiaLWkoH8eUgA8BqIL4De7083nVVdht/b8rva+IYWSrBom6BhlOtulOSVofEvKSLK2Q8DjPbO4FnD3rwfdW5FZss8RWXP1I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=cMMocopL; arc=none smtp.client-ip=79.135.106.30 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="cMMocopL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1771591748; x=1771850948; bh=wNaWXhcxNfHnH6HkOZF3gD/FvPmA6p8/4mrbsx0sDPw=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=cMMocopLazeC8+tZE97ZKcNU659PZl8XVsQ2DBKwnIETtvB+KHX8WqU1nOWAVUCq/ bBrvGkTz1w1UdW01QEarw5MsjFm40f2oZiwWmSni3QXSsmo3xriqmE8rNd6bVCIeW2 4OvclgnTrOT6DCH2I/wG3alzT/ocnC0vQ340O/owQWsHhkc9R7tF9XgY1X2hK7D6ZG qaubgkatu9CVDvfu2Q7O8X65e6dryvMz5osR8JpBImq6FDG5eijxnJUvb3wKSF5bYe cYmS3u1jt5OENZPw7l6xDDNC3u6JGpHL2j6mYZMHS3uAPizm/XuocEiJ0aQbtbJ/pE FqhgsdaqccH9A== Date: Fri, 20 Feb 2026 12:48:56 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , linux-kernel@vger.kernel.org Subject: [PATCH v1 3/4] x86/mm: Cleanup comments where LAM_U48 is mentioned Message-ID: <6910307be0078e5981001cf1f3bb1a520040082c.1771589807.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 26fd3b226a2cbfb2f298ef1f6a7027f263b561a0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman For simplicity only the LAM_U57 mode is implemented in the kernel. No matter whether the enabled paging mode is 5-level or 4-level the masked tag bits are the same as on a 5-level system. Remove two mentions of LAM_U48 which implied that it could be enabled. Signed-off-by: Maciej Wieczor-Retman --- arch/x86/include/asm/mmu.h | 2 +- arch/x86/include/asm/tlbflush.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 0fe9c569d171..9dcfce439c19 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -49,7 +49,7 @@ typedef struct { unsigned long flags; =20 #ifdef CONFIG_ADDRESS_MASKING - /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ + /* Active LAM mode: X86_CR3_LAM_U57 or 0 (disabled) */ unsigned long lam_cr3_mask; =20 /* Significant bits of the virtual address. Excludes tag bits. */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 00daedfefc1b..fe6458619f64 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -110,7 +110,7 @@ struct tlb_state { /* * Active LAM mode. * - * X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM + * X86_CR3_LAM_U57 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM * disabled. */ u8 lam; --=20 2.53.0