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Thu, 18 Dec 2025 13:43:26 -0800 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH rc v5 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Date: Thu, 18 Dec 2025 13:41:59 -0800 Message-ID: <68d48a88a64223a1d9b76b59c05f4743f1953c9c.1766093909.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055E1:EE_|IA0PPF4D923B935:EE_ X-MS-Office365-Filtering-Correlation-Id: ad92a22a-102a-4143-0cac-08de3e7e850a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?3+zXfDJEBcrnxFEe8OCqycazJ5j+Yc0FtKXZ0WJWz9U6fWz1YoDzqJXzqn+P?= =?us-ascii?Q?4ET75NCu6YTUVXd4eGixcOWwcsWQ43YhGW+5vNAPVhVDtuTjlfCT9UHbwK8m?= =?us-ascii?Q?ICnPmBKnRTihGNogGSO0LwLMpwdOh9mGxwplwoqPkOq3ECc62jhNA+xuEWcw?= =?us-ascii?Q?WVkRTBizsyKf+vWCt4aG9TfBlZ+hHTsqCAEzyDXObF1qTBxofWvdcVr4ScXJ?= =?us-ascii?Q?BN2yQFriERqqh89v8xImryOb0Jy7eaJ1EFSNZOIPI4DWxJoJtJ79WSuKsDx4?= =?us-ascii?Q?BozF3nxBEYvi/wzeqQ7SaEST9pBr/8pmj2V2D5v8ggpxtH42nFpYPGjV93gb?= =?us-ascii?Q?wo0UFhYeYWf3YTAcf/L2Vzt0+0tKe2tjOptyNNjNRrX8LNUI0+8TVLUt7ZTW?= =?us-ascii?Q?TqH9MFLnudYxaFM4kJ1L87TMPVJO8AN8mCzVeZKZvBYW0baxPZ23B5c+VjC4?= =?us-ascii?Q?eVuL5UWMH4Qxh9Fi6JzRcGRqbtuep7HY7iR8iUS52GJM84EUCZODWdxqdm2H?= =?us-ascii?Q?dm8q8E+Bt/1Q7XshqUG1D+1ARrz7gLWgMIe8BINrvnikRlLWm76RZcMdLEDl?= =?us-ascii?Q?fmTZwOw1T/GDqUVWlMCAtB7CsR6KGsxvOQdCVscPeag5kpcThEgE9BB65mAV?= =?us-ascii?Q?9ZK3DM0OpLblenAIg5UxgwKMc2uXfyUWkWeHtoyaEOSw3xDY9DaIVmUC/L3c?= =?us-ascii?Q?WQfVHnf3lQAAms/LUa6iIrXLtot9wSYbnispLXd8PQUKCbEgk8bUv9MRb1yY?= =?us-ascii?Q?2hFSESRY4YdQToyqqFruP7aYwPa9oWVVWNjbe1wYyO+17vSgkjJjSI655RW9?= =?us-ascii?Q?w1npi5WBzKYrxYRypK5FlhKph4pIm8nA3ivSmO2RUtI5418X6iLWOSZlj02E?= =?us-ascii?Q?7ej15ClS6666NBFmP5Yvwf7pbs2Bexfw92OKRg4fhWNPtpwPV77MJn10TwXC?= =?us-ascii?Q?lA6JE18CvI2fq4VZRojYHvRErokVab/59M7ynm8fL0xCSC4Jz5ZcvN0de6UL?= =?us-ascii?Q?RveUdM/HSwRlFs1j5a/0IHlyf6u1d2d3CnlZ9Bzg3ITqD16tbK51Od2um4Ay?= =?us-ascii?Q?3Sjr3FrS8WWU4t/FneHXEF0RqDOI+TvQxyLIFt3GAFBUG6hakFnzKr265loI?= =?us-ascii?Q?AZ7kX6mBSKx6gV67Msp5HfufPLuYx5iPVn5g0beg7mtihgIaWbx6P7UxNVlp?= =?us-ascii?Q?dCacQj5oeo6omh7KYzxAdQcGFLAyq6ZeXMBa62l6fZCzuMLu3hmcwtVsv84W?= =?us-ascii?Q?t6dXnpqzRp9aXnQD/9MizlGXyO741jeM//ggqIw+GoNx6hiIzs1Fh03NOYHf?= =?us-ascii?Q?nBY4QRn1gfm6XCHKLTN4DqOwUOAazDvuG2LpRyWA5OCvEMv9tgIOUrHvJcn6?= =?us-ascii?Q?oHZ0e5hCDFRgChfFAcRXr+xtmApW4HxS5Jo3sXuvWLDiicFhuvgKJ4jOD/3i?= =?us-ascii?Q?VF0Ef829joLyJ51BQezLV27mrwsNXvK7cudN/FqW437rTY7yfsiJ0D6WnV6G?= =?us-ascii?Q?k0T6eWyobms0i3TDOrKkb1sLrOjRWZuZiqXQuiKcJQDh/CtdGulqQ88z9r4E?= =?us-ascii?Q?7bdVJ2NGPgLYTRL14eE=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 21:43:45.0286 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad92a22a-102a-4143-0cac-08de3e7e850a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055E1.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPF4D923B935 Content-Type: text/plain; charset="utf-8" STE in a nested case requires both S1 and S2 fields. And this makes the use case different from the existing one. Add coverage for previously failed cases shifting between S2-only and S1+S2 STEs. Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 5db14718fdd6..4a072c2c367c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -33,8 +33,12 @@ static struct mm_struct sva_mm =3D { enum arm_smmu_test_master_feat { ARM_SMMU_MASTER_TEST_ATS =3D BIT(0), ARM_SMMU_MASTER_TEST_STALL =3D BIT(1), + ARM_SMMU_MASTER_TEST_NESTED =3D BIT(2), }; =20 +static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, + enum arm_smmu_test_master_feat feat); + static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, const __le64 *target, @@ -197,6 +201,18 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_= smmu_ste *ste, }; =20 arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); + if (feat & ARM_SMMU_MASTER_TEST_NESTED) { + struct arm_smmu_ste s2ste; + int i; + + arm_smmu_test_make_s2_ste(&s2ste, + feat & ~ARM_SMMU_MASTER_TEST_NESTED); + ste->data[0] |=3D cpu_to_le64( + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); + ste->data[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); + for (i =3D 2; i < NUM_ENTRY_QWORDS; i++) + ste->data[i] =3D s2ste.data[i]; + } } =20 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) @@ -554,6 +570,35 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(= struct kunit *test) NUM_EXPECTED_SYNCS(3)); } =20 +static void +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + /* Expect an additional sync to unset ignored bits: EATS and MEV */ + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(2)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -600,6 +645,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.43.0