From nobody Thu Oct 2 10:53:01 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 38DEA24BBFD; Thu, 18 Sep 2025 16:50:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214250; cv=none; b=NAEYGjZIfyfP9XEQ2FVCjpj0iKHcH6fDoK25XdZj+gpx36PJN3ht1CRgyd08RbNfY8mZZ0JxJzs1o4UYv/L7OpJlr2A3sk+9eQedpLBo9ugh6wBkYeDCtU+9ZPv0MhONrub+Bb/nWv0HupOhFyW+WHHriPBsM2hQ1wk2MbNy9ro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214250; c=relaxed/simple; bh=LLw9e41r3Nu4RX42WVov9+WnfXYO1+RpidnMUsA7kyA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tfZP4TuEwQWiqvw3gMP6Wa//2LrCOQTBdOBcmwW4jJv8HiXVgl9ga/G7PKDX14vWRJPwclF2Dr9RnH+BXnh2bGZeHsegrIzEKPrUKEDvHO2Kw/dWROB6/noeGKc9mWyYPt4avULq9egTIleGhL0Lqp0t9H+LXDszepwy5VGYJuc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cSLY61dgCz9sg4; Thu, 18 Sep 2025 18:23:38 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bWMfx8aSixG3; Thu, 18 Sep 2025 18:23:38 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cSLY45WG2z9sfq; Thu, 18 Sep 2025 18:23:36 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id AAACE8B767; Thu, 18 Sep 2025 18:23:36 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id cycSslAEFx8u; Thu, 18 Sep 2025 18:23:36 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id EC5308B776; Thu, 18 Sep 2025 18:23:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Conor Dooley Subject: [PATCH v6 5/7] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Thu, 18 Sep 2025 18:23:25 +0200 Message-ID: <67987bbf42344398709949cb53e3e8415260ec09.1758212309.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212605; l=2384; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=LLw9e41r3Nu4RX42WVov9+WnfXYO1+RpidnMUsA7kyA=; b=YDDPEKiP3Ihfi8Pm7o7zYRnNRvlYkYvxNfNQKaJ78/6tLwk/gZeiVWgFd34JlEKpPkQz5YuNm 7q+0fY29QL+CIgPgMa30z7I7M2Y68WpSf6wgo9LrLQ1Iy4lQ7igZ528 X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. Acked-by: Conor Dooley Signed-off-by: Christophe Leroy --- .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe= -ports-ic.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-= ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.= yaml new file mode 100644 index 000000000000..a356ad8b13f5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - Christophe Leroy + +description: + Interrupt controller for the QUICC Engine I/O ports found on some Freesc= ale/NXP PowerQUICC and QorIQ SoCs. + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + - fsl,mpc8360-qe-ports-ic + - fsl,mpc8568-qe-ports-ic + + reg: + maxItems: 1 + description: Base address and size of the QE I/O Ports Interrupt Contr= oller registers. + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + description: Interrupt line to which the QE I/O Ports controller is co= nnected. + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@c00 { + compatible =3D "fsl,mpc8323-qe-ports-ic"; + reg =3D <0xc00 0x18>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupts =3D <74 0x8>; + interrupt-parent =3D <&ipic>; + }; --=20 2.49.0