From nobody Tue Oct 7 11:45:06 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD84F2FCFF9; Thu, 10 Jul 2025 20:07:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178064; cv=none; b=TTTklaQWnN1jdH9TRB/cEshnaTH6+t3F7C5l/NXQIClwFjltJ+u/wYoalQY0lzE+fu999tjoP3vDwErhD0+Wgw2FXX3UVk7lT02cdpo7iRTGE9B/O3Kzi1XYqIQMmCnhsxP/MV6I+dBvK1g0/j1+wjSD2NEbNSPcBeq58iSd0q0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178064; c=relaxed/simple; bh=oKAR3NS0HjQgRq/Kuii8R5KT6JT9p0LPD92K1751Fik=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JW0flo1nCvBclXk8gXnnu8mZz3P780khkNJcBAECxfIPUCcTKA+KApRSUAlc/b9fbfy05dCuy4JwrU5cGRjEDuflq8ym32LFC9MrnyoywgbLNIn6A+XqrJpKZraQm5x4CKc3Iqxv3NMlTYYU/RlpNS1wPe3lb9Mu61htuzAQk04= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=gCxQ6VUS; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="gCxQ6VUS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1752178063; x=1783714063; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oKAR3NS0HjQgRq/Kuii8R5KT6JT9p0LPD92K1751Fik=; b=gCxQ6VUSz7pdcFHH82YtaRr13AMwIey3lOXc8XxifV+JNR3ldOcXhixn e3eSje4gD6msGE74pyCl9GrsLtryZ3lr7w+tBaIs2s62XYNupxJ9Xkn/b mcn8yQCC+zBRcZc09H8zdQaFI8miDy44nyAvkZIVqLKSlhgXgkH6rZ7Zh tO/ue0xNjRM0KMJqc03AWRlJDcQxvmRWOPP6dsx6z4YtnsRDSka77uDjV rX+en0anauDsDQVdn9N3aqL0f8srdveRFyZaTYDOEjX10mU+v69KZ+/53 09a5HWzXI3Z6IQkTNCOf/gdUrf9NUE+c8RlArUE6XvWKgvYUFe8WCZXg4 Q==; X-CSE-ConnectionGUID: qOQSLemoQZOGUxBCHa7nXg== X-CSE-MsgGUID: vxnueUJPRy2Fdmu5gqCu9Q== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="275215671" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:32 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:32 -0700 From: To: , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v3 13/32] clk: at91: sama7d65: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:07:06 -0700 Message-ID: <676e618850df0db8dd880c36cd9b6dcef7b17b8b.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Switch the system clocks to use parent_hw and parent_data. Having this allows the driver to conform to the new clk-system API. The parent registration is after the USBCK registration due to one of the system clocks being dependent on USBCK. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7d65.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index f10faabc7ffe..1553dc3152a4 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -533,23 +533,23 @@ static struct { /* * System clock description * @n: clock name - * @p: clock parent name + * @p: clock parent hw * @id: clock id */ -static const struct { +static struct { const char *n; - const char *p; + struct clk_hw *parent_hw; u8 id; } sama7d65_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8, }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9, }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10, }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11, }, - { .n =3D "pck4", .p =3D "prog4", .id =3D 12, }, - { .n =3D "pck5", .p =3D "prog5", .id =3D 13, }, - { .n =3D "pck6", .p =3D "prog6", .id =3D 14, }, - { .n =3D "pck7", .p =3D "prog7", .id =3D 15, }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8, }, + { .n =3D "pck1", .id =3D 9, }, + { .n =3D "pck2", .id =3D 10, }, + { .n =3D "pck3", .id =3D 11, }, + { .n =3D "pck4", .id =3D 12, }, + { .n =3D "pck5", .id =3D 13, }, + { .n =3D "pck6", .id =3D 14, }, + { .n =3D "pck7", .id =3D 15, }, }; =20 /* Mux table for programmable clocks. */ @@ -1283,10 +1283,19 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) =20 sama7d65_pmc->pchws[i] =3D hw; } - + /* Set systemck parent hws. */ + sama7d65_systemck[0].parent_hw =3D usbck_hw; + sama7d65_systemck[1].parent_hw =3D sama7d65_pmc->pchws[0]; + sama7d65_systemck[2].parent_hw =3D sama7d65_pmc->pchws[1]; + sama7d65_systemck[3].parent_hw =3D sama7d65_pmc->pchws[2]; + sama7d65_systemck[4].parent_hw =3D sama7d65_pmc->pchws[3]; + sama7d65_systemck[5].parent_hw =3D sama7d65_pmc->pchws[4]; + sama7d65_systemck[6].parent_hw =3D sama7d65_pmc->pchws[5]; + sama7d65_systemck[7].parent_hw =3D sama7d65_pmc->pchws[6]; + sama7d65_systemck[8].parent_hw =3D sama7d65_pmc->pchws[7]; for (i =3D 0; i < ARRAY_SIZE(sama7d65_systemck); i++) { hw =3D at91_clk_register_system(regmap, sama7d65_systemck[i].n, - sama7d65_systemck[i].p, NULL, + NULL, &AT91_CLK_PD_HW(sama7d65_systemck[i].parent_hw), sama7d65_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; --=20 2.43.0