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[93.144.20.233]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-487271be661sm11252605e9.35.2026.03.27.02.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 02:09:10 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shawn Guo , Dario Binacchi , Alexander Stein , Maud Spierings , Josua Mayer , Markus Niebel , Primoz Fiser , Francesco Dolcini Subject: [PATCH v2 3/3] arm64: dts: imx93-var-dart: Add support for Variscite Sonata board Date: Fri, 27 Mar 2026 10:08:56 +0100 Message-ID: <676acc750ecc1c467bedf4f09996537c2716cafa.1774601806.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite Sonata carrier board with the DART-MX93 system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli --- v1->v2: -=20 arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-var-dart-sonata.dts | 654 ++++++++++++++++++ 2 files changed, 655 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 2da6dc4f8a14..266eddd745c9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -487,6 +487,7 @@ imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs :=3D imx9= 3-tqma9352-mba91xxca.dtb im dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb =20 +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx943-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts b/arch= /arm64/boot/dts/freescale/imx93-var-dart-sonata.dts new file mode 100644 index 000000000000..5513d3b148a2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts @@ -0,0 +1,654 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX93 + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include "imx93-var-dart.dtsi" + +/ { + model =3D "Variscite DART-MX93 on Sonata-Board"; + compatible =3D "variscite,var-dart-mx93-sonata", + "variscite,var-dart-mx93", + "fsl,imx93"; + + aliases { + ethernet0 =3D &eqos; + ethernet1 =3D &fec; + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + i2c3 =3D &lpi2c4; + i2c4 =3D &lpi2c5; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart1; + serial1 =3D &lpuart2; + serial2 =3D &lpuart3; + serial3 =3D &lpuart4; + serial4 =3D &lpuart5; + serial5 =3D &lpuart6; + serial6 =3D &lpuart7; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-home { + label =3D "Home"; + linux,code =3D ; + gpios =3D <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label =3D "Up"; + linux,code =3D ; + gpios =3D <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label =3D "Down"; + linux,code =3D ; + gpios =3D <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label =3D "Back"; + linux,code =3D ; + gpios =3D <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_leds_gpio>; + + led-emmc { + gpios =3D <&gpio2 11 GPIO_ACTIVE_HIGH>; + label =3D "eMMC"; + linux,default-trigger =3D "mmc0"; + }; + }; + + clk40m: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <40000000>; + clock-output-names =3D "can_osc"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_1v8"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_SD2_3V3"; + off-on-delay-us =3D <20000>; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ethosu_mem: ethosu-region@88000000 { + compatible =3D "shared-dma-pool"; + reusable; + reg =3D <0x0 0x88000000 0x0 0x8000000>; + }; + + vdev0vring0: vdev0vring0@87ee0000 { + reg =3D <0 0x87ee0000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@87ee8000 { + reg =3D <0 0x87ee8000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@87ef0000 { + reg =3D <0 0x87ef0000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@87ef8000 { + reg =3D <0 0x87ef8000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg =3D <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@87f00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x87f00000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@87de0000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x87de0000 0 0x100000>; + no-map; + }; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +/* Use external instead of internal RTC */ +&bbnsm_rtc { + status =3D "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-assert-us =3D <15000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&pca6408_2 0 GPIO_ACTIVE_LOW>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + }; + }; + }; +}; + +ðphy0 { + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + }; +}; + +&fec { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_fec>; + pinctrl-1 =3D <&pinctrl_fec_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy1>; + status =3D "okay"; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + status =3D "okay"; +}; + +&lpi2c1 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c1_gpio>; + pinctrl-names =3D "default", "sleep", "gpio"; + scl-gpios =3D <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pca9534: gpio@22 { + compatible =3D "nxp,pca9534"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible =3D "edt,edt-ft5206"; + reg =3D <0x38>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 =3D <&pinctrl_captouch>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pca6408_2 4 GPIO_ACTIVE_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-size-x =3D <800>; + touchscreen-size-y =3D <480>; + wakeup-source; + }; + + /* USB Type-C Controller */ + typec@3d { + compatible =3D "nxp,ptn5150"; + reg =3D <0x3d>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 =3D <&pinctrl_extcon>; + pinctrl-names =3D "default"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint =3D <&usb1_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible =3D "dallas,ds1337"; + reg =3D <0x68>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rtc>; + wakeup-source; + }; +}; + +&lpi2c5 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c5>; + pinctrl-1 =3D <&pinctrl_lpi2c5_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c5_gpio>; + scl-gpios =3D <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&lpi2c7 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c7>; + pinctrl-1 =3D <&pinctrl_lpi2c7_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c7_gpio>; + scl-gpios =3D <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pca6408_1: gpio@20 { + compatible =3D "nxp,pcal6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible =3D "nxp,pcal6408"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible =3D "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg =3D <0x2e>; + }; +}; + +&lpspi8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi8>; + cs-gpios =3D <&gpio2 1 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + /* CAN controller */ + can0: can@0 { + compatible =3D "microchip,mcp251xfd"; + reg =3D <0>; + clocks =3D <&clk40m>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + spi-max-frequency =3D <1000000>; + }; +}; + +/* Console (J10) */ +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +/* Header (J12.4, J12.6) */ +&lpuart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart6>; + status =3D "okay"; +}; + +/* Header (J12.11, J12.13) */ +&lpuart7 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart7>; + status =3D "okay"; +}; + +&tpm3 { + pinctrl-0 =3D <&pinctrl_tpm3>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control =3D <3>; + samsung,picophy-dc-vol-level-adjust =3D <7>; + status =3D "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint =3D <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode =3D "host"; + status =3D "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + no-sdio; + no-mmc; + status =3D "okay"; +}; + +&wdog3 { + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_can: cangrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x37e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins =3D < + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + /* GPIO Expanders shared IRQ */ + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_leds_gpio: ledgrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO11__GPIO2_IO11 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c5_gpio: lpi2c5-gpiogrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x40000b9e + MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO07__GPIO2_IO07 0x31e + MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e + >; + }; + + pinctrl_lpspi8: lpspi8grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e + MX93_PAD_GPIO_IO12__GPIO2_IO12 0x31e + MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x31e + MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e + MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e + MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; --=20 2.47.3