From nobody Thu Dec 18 06:30:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40CD3C71145 for ; Thu, 24 Aug 2023 09:21:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240272AbjHXJVU (ORCPT ); Thu, 24 Aug 2023 05:21:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240705AbjHXJUx (ORCPT ); Thu, 24 Aug 2023 05:20:53 -0400 Received: from jari.cn (unknown [218.92.28.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4C18FE67 for ; Thu, 24 Aug 2023 02:20:46 -0700 (PDT) Received: from chenxuebing$jari.cn ( [125.70.163.142] ) by ajax-webmail-localhost.localdomain (Coremail) ; Thu, 24 Aug 2023 17:20:17 +0800 (GMT+08:00) X-Originating-IP: [125.70.163.142] Date: Thu, 24 Aug 2023 17:20:17 +0800 (GMT+08:00) X-CM-HeaderCharset: UTF-8 From: "XueBing Chen" To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amdgpu/sdma: Clean up errors in sdma_v3_0.c X-Priority: 3 X-Mailer: Coremail Webmail Server Version 2023.1-cmXT6 build 20230419(ff23bf83) Copyright (c) 2002-2023 www.mailtech.cn mispb-4e503810-ca60-4ec8-a188-7102c18937cf-zhkzyfz.cn Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Message-ID: <662fba8d.647.18a26d833dc.Coremail.chenxuebing@jari.cn> X-Coremail-Locale: zh_CN X-CM-TRANSID: AQAAfwC3VUDRIOdkwFeSAA--.475W X-CM-SenderInfo: hfkh05pxhex0nj6mt2flof0/1tbiAQANCmTl1A4APAAIsp X-Coremail-Antispam: 1Ur529EdanIXcx71UUUUU7IcSsGvfJ3iIAIbVAYjsxI4VWxJw CS07vEb4IE77IF4wCS07vE1I0E4x80FVAKz4kxMIAIbVAFxVCaYxvI4VCIwcAKzIAtYxBI daVFxhVjvjDU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line ERROR: trailing statements should be on next line Signed-off-by: XueBing Chen --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 42 +++++++++----------------- 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/a= mdgpu/sdma_v3_0.c index 344202870aeb..2e70e2caa353 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -71,14 +71,12 @@ MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); =20 =20 -static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =3D -{ +static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =3D { SDMA0_REGISTER_OFFSET, SDMA1_REGISTER_OFFSET }; =20 -static const u32 golden_settings_tonga_a11[] =3D -{ +static const u32 golden_settings_tonga_a11[] =3D { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -91,14 +89,12 @@ static const u32 golden_settings_tonga_a11[] =3D mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; =20 -static const u32 tonga_mgcg_cgcg_init[] =3D -{ +static const u32 tonga_mgcg_cgcg_init[] =3D { mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; =20 -static const u32 golden_settings_fiji_a10[] =3D -{ +static const u32 golden_settings_fiji_a10[] =3D { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, @@ -109,14 +105,12 @@ static const u32 golden_settings_fiji_a10[] =3D mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; =20 -static const u32 fiji_mgcg_cgcg_init[] =3D -{ +static const u32 fiji_mgcg_cgcg_init[] =3D { mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; =20 -static const u32 golden_settings_polaris11_a11[] =3D -{ +static const u32 golden_settings_polaris11_a11[] =3D { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -129,8 +123,7 @@ static const u32 golden_settings_polaris11_a11[] =3D mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; =20 -static const u32 golden_settings_polaris10_a11[] =3D -{ +static const u32 golden_settings_polaris10_a11[] =3D { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -143,8 +136,7 @@ static const u32 golden_settings_polaris10_a11[] =3D mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; =20 -static const u32 cz_golden_settings_a11[] =3D -{ +static const u32 cz_golden_settings_a11[] =3D { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, @@ -159,22 +151,19 @@ static const u32 cz_golden_settings_a11[] =3D mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, }; =20 -static const u32 cz_mgcg_cgcg_init[] =3D -{ +static const u32 cz_mgcg_cgcg_init[] =3D { mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; =20 -static const u32 stoney_golden_settings_a11[] =3D -{ +static const u32 stoney_golden_settings_a11[] =3D { mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, }; =20 -static const u32 stoney_mgcg_cgcg_init[] =3D -{ +static const u32 stoney_mgcg_cgcg_init[] =3D { mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, }; =20 @@ -300,7 +289,8 @@ static int sdma_v3_0_init_microcode(struct amdgpu_devic= e *adev) case CHIP_STONEY: chip_name =3D "stoney"; break; - default: BUG(); + default: + BUG(); } =20 for (i =3D 0; i < adev->sdma.num_instances; i++) { @@ -1702,8 +1692,7 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_= device *adev) adev->vm_manager.vm_pte_num_scheds =3D adev->sdma.num_instances; } =20 -const struct amdgpu_ip_block_version sdma_v3_0_ip_block =3D -{ +const struct amdgpu_ip_block_version sdma_v3_0_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, .major =3D 3, .minor =3D 0, @@ -1711,8 +1700,7 @@ const struct amdgpu_ip_block_version sdma_v3_0_ip_blo= ck =3D .funcs =3D &sdma_v3_0_ip_funcs, }; =20 -const struct amdgpu_ip_block_version sdma_v3_1_ip_block =3D -{ +const struct amdgpu_ip_block_version sdma_v3_1_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_SDMA, .major =3D 3, .minor =3D 1, --=20 2.17.1