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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:24:29.2267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b6e34f4-66c9-4c69-4a8f-08ddc5eda930 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6246 Content-Type: text/plain; charset="utf-8" The kit based on K26 SOM is built for robotics and industrial application. Signed-off-by: Michal Simek --- https://www.amd.com/en/products/system-on-modules/kria/k26/kr260-robotics-s= tarter-kit.html --- arch/arm64/boot/dts/xilinx/Makefile | 9 + .../boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 438 +++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 451 ++++++++++++++++++ 3 files changed, 898 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xili= nx/Makefile index 7f5a8801cad1..5e84e3c725e2 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -30,4 +30,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-k= v-g-revA.dtb zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kv-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kv-g-revB.dtb =20 +zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs :=3D zynqmp-sm-k26-revA.dtb zynqmp-s= ck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k26-revA-sck-kr-g-revA.dtb +zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs :=3D zynqmp-sm-k26-revA.dtb zynqmp-s= ck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k26-revA-sck-kr-g-revB.dtb +zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kr-g-revA.dtb +zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) +=3D versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/ar= m64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso new file mode 100644 index 000000000000..fbacfa984d76 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revA Carrier Card + * + * (C) Copyright 2021, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible =3D "xlnx,zynqmp-sk-kr260-revA", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model =3D "ZynqMP KR260 revA"; + + aliases { + ethernet0 =3D "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 =3D "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u14 { + compatible =3D "iio-hwmon"; + io-channels =3D <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_27: clock0 { /* u86 - DP */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <27000000>; + }; + + clk_125: si5332-0 { /* u17 - GEM0/1 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + clk_74: si5332-5 { /* u17 - SLVC-EC */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <74250000>; + }; + + clk_26: si5332-2 { /* u17 - USB */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + }; + + clk_156: si5332-3 { /* u17 - SFP+ */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <156250000>; + }; + + clk_25_0: si5332-1 { /* u17 - GEM2 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_25_1: si5332-4 { /* u17 - GEM3 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1_default>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible =3D "ti,ina260"; + #io-channel-cells =3D <1>; + label =3D "ina260-u14"; + reg =3D <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible =3D "dlg,slg7xl45106"; + reg =3D <0x11>; + label =3D "resetchip"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible =3D "nxp,pca9546"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + hub_1: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + hub_2: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status =3D "okay"; + /* gem0/1, dp, usb */ + clocks =3D <&clk_125>, <&clk_27>, <&clk_26>; + clock-names =3D "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status =3D "okay"; + phy-names =3D "dp-phy0"; + phys =3D <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates =3D <27000000>, <25000000>, <300000000>; +}; + +&zynqmp_dpdma { + status =3D "okay"; + assigned-clock-rates =3D <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb0_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios =3D <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_0 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios =3D <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_1 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub1_3_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub1_2_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status =3D "okay"; + phys =3D <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle =3D <&phy0>; + phy-mode =3D "sgmii"; + assigned-clock-rates =3D <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gem1_default>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + assigned-clock-rates =3D <250000000>; + + mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <4>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <300>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <8>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <100>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status =3D "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups =3D "uart1_9_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups =3D "uart1_9_grp"; + function =3D "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups =3D "i2c1_6_grp"; + bias-pull-up; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "i2c1_6_grp"; + function =3D "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + function =3D "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups =3D "ethernet1_0_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins =3D "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins =3D "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups =3D "mdio1_0_grp"; + slew-rate =3D ; + power-source =3D ; + bias-disable; + output-enable; + }; + + mux-mdio { + function =3D "mdio1"; + groups =3D "mdio1_0_grp"; + }; + + mux { + function =3D "ethernet1"; + groups =3D "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups =3D "usb0_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb0_0_grp"; + function =3D "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups =3D "usb1_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb1_0_grp"; + function =3D "usb1"; + }; + }; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1_default>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/ar= m64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso new file mode 100644 index 000000000000..b7cda216b179 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revB Carrier Card (A03 revision) + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible =3D "xlnx,zynqmp-sk-kr260-revB", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model =3D "ZynqMP KR260 revB"; + + ina260-u14 { + compatible =3D "iio-hwmon"; + io-channels =3D <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_125: clock0 { /* u87 - GEM0/1 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + clk_27: clock1 { /* u86 - DP */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <27000000>; + }; + + clk_26: clock2 { /* u89 - USB */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + }; + + clk_156: clock3 { /* u90 - SFP+ */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <156250000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_74: clock6 { /* u88 - SLVC-EC */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <74250000>; + }; + + dpcon { + compatible =3D "dp-connector"; + label =3D "P11"; + type =3D "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint =3D <&dpsub_dp_out>; + }; + }; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1_default>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible =3D "ti,ina260"; + #io-channel-cells =3D <1>; + label =3D "ina260-u14"; + reg =3D <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible =3D "dlg,slg7xl45106"; + reg =3D <0x11>; + label =3D "resetchip"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible =3D "nxp,pca9546"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + hub_1: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + hub_2: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status =3D "okay"; + /* gem0/1, dp, usb */ + clocks =3D <&clk_125>, <&clk_27>, <&clk_26>; + clock-names =3D "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status =3D "okay"; + phy-names =3D "dp-phy0"; + phys =3D <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates =3D <27000000>, <25000000>, <300000000>; +}; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint =3D <&dpcon_in>; + }; +}; + +&zynqmp_dpdma { + status =3D "okay"; + assigned-clock-rates =3D <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb0_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios =3D <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_0 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios =3D <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_1 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub1_3_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub1_2_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status =3D "okay"; + phys =3D <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle =3D <&phy0>; + phy-mode =3D "sgmii"; + assigned-clock-rates =3D <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gem1_default>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + assigned-clock-rates =3D <250000000>; + + mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <4>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <300>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <8>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <100>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status =3D "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups =3D "uart1_9_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups =3D "uart1_9_grp"; + function =3D "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups =3D "i2c1_6_grp"; + bias-pull-up; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "i2c1_6_grp"; + function =3D "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + function =3D "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups =3D "ethernet1_0_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins =3D "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins =3D "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups =3D "mdio1_0_grp"; + slew-rate =3D ; + power-source =3D ; + bias-disable; + output-enable; + }; + + mux-mdio { + function =3D "mdio1"; + groups =3D "mdio1_0_grp"; + }; + + mux { + function =3D "ethernet1"; + groups =3D "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups =3D "usb0_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb0_0_grp"; + function =3D "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups =3D "usb1_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb1_0_grp"; + function =3D "usb1"; + }; + }; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1_default>; +}; --=20 2.43.0