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Fri, 13 Jun 2025 23:35:40 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , , Subject: [PATCH v2 10/14] iommu/arm-smmu-v3: Replace arm_vsmmu_alloc with arm_vsmmu_init Date: Fri, 13 Jun 2025 23:35:22 -0700 Message-ID: <64e4b4c33acd26e1bd676e077be80e00fb63f17c.1749882255.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E3:EE_|PH0PR12MB7790:EE_ X-MS-Office365-Filtering-Correlation-Id: 0feb6dce-9194-4c00-a9fb-08ddab0db7ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NaPRCOSrYffE8bSskY48q8ijD75nSuWAd2ZpubTMt+ZE7u5U/0sWI5b7+DH1?= =?us-ascii?Q?IVSiAzm+hasw8sQ9cKdGlQlKkvi+Ztco0qwyFsvI6XivRwcRjNpam5056Rm5?= =?us-ascii?Q?W1GYsMULVCCRUXfFZkf9aDdTIabCpA5kn0CfBQaV5uIa9fU/OhKeaMcZF/eu?= =?us-ascii?Q?LtVsxHCydMQFaHPumLi5lG6l8JA2YmuNivKzng2gm+zOXCPEzzkPGrp/R9/S?= =?us-ascii?Q?aHxXqGGmgHAVxaxQ1ZytBU1wHlc8at1cn4z37aSIS0vG/L1Y6v0WNIyUGGac?= =?us-ascii?Q?GJ5VAzXKcI5Cd2uVAvJeuDyLkBffJxL+B6xfaaAZLdgSVPakFppPAs15y5le?= =?us-ascii?Q?LrHvojoRrHWi8wrSpjtX0bYzjheXkhq+tukQuW/NIqC7/eEB8Dpco8JDjj1Q?= =?us-ascii?Q?tbHA/jZ6Ecf58zLPF/nxrqoKP8J10dX5UpyMH4Z840YpSk0OtGJ/9PhNPaoI?= =?us-ascii?Q?X7DA6ZcXgEULj/rnX95aVi4HIHxfR/b5aDNmAlUy2JYy2UWo4OwTxqRKYVF3?= =?us-ascii?Q?4AVi/zLPotOoPHBvy5oJH21xho1FWSPTx9iZqLq5OsJadu3rcuSf1Ktm0j/x?= =?us-ascii?Q?l7Hh6ZP5xRHwI4qPP14T1xnAaKu3NMPFrIq2Fx6kw59BTZzLr68M3Jt8Qbs9?= =?us-ascii?Q?eOa73W+p55amzYod+CHQxGcZcpoOXAO5uIHL1h50ncO2dhQklBO1966ECHm0?= =?us-ascii?Q?d+q7GsJ32yYDFz4DELNqAtr1f6s0/AdasUeC2EIId4hIGt1+MzrI/OgvePPQ?= =?us-ascii?Q?TcSXD0ETNtA+mr5K+W68/WT9RemHLsOT1GTjFHS+b3n7qIBOZWuKpPvjzmKZ?= =?us-ascii?Q?4x0/EUJhYZ/meecJUaoutfZS3ZVx14BlEEaWPgeoXrOMeSq+qtv8nV5yEE/I?= =?us-ascii?Q?KJ+M2qYt2WQH9vDCCxw8KdhLRiua419BlaM50Lwb2OGNFGrS8NTU+EcV9p4B?= =?us-ascii?Q?nRBvMfQwQ907/sylK2g83vr1LsU7/jOPeOPhT9hP4dbWOW7fwC6/CbYEhDAy?= =?us-ascii?Q?71ujxfqhgiJ6goFRO6PcKHNK3vzSfDhuUft9/VA/4g52kMVG/QqxbApL/YVb?= =?us-ascii?Q?4dreufa2QZl2cPjag7GOnQu9vCGKWjfJ9z/BKyY4a2lRJmppPjC1WTExEWJw?= =?us-ascii?Q?dtmsSDoIf1t3iJ4iGIlhA1b18vyOM1lVBWpkZw8M8FZzCCiQqBfVvSC1lcsZ?= =?us-ascii?Q?YnMiiixFIBA75NjlLJ09BKw9rfC3mWROB/UyUWgiSWIn2kdakOmzq35cIjVY?= =?us-ascii?Q?grgknhOJUm5Se3jLBtypwVlW1714nlsS8C2iz3qY6L0F7T66FS5OXN0hvlVu?= =?us-ascii?Q?NcBpBfvghHh5h4tY9JXZZp4qK6Lf4iyq+N8ew2dvex/CDVkT8jm32Ovc+snJ?= =?us-ascii?Q?IWdifA1zW9RhOcgUIQJlJg8bpTXVdmQCTBZEcWhDrMmRhRaT2VyFelUeomNX?= =?us-ascii?Q?b8yCpqe0S7hVne2SpoX73yDp4AcKSAkru9QONQKGr1l0q95cfhpipQuxiSpY?= =?us-ascii?Q?TmH0VdWNyUfvDm2ZbLOyCQPSGRZaAcF/PLFu?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2025 06:35:56.3032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0feb6dce-9194-4c00-a9fb-08ddab0db7ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7790 Content-Type: text/plain; charset="utf-8" To ease the for-driver iommufd APIs, get_viommu_size and viommu_init ops are introduced. Sanitize the inputs and report the size of struct arm_vsmmu on success, in arm_smmu_get_viommu_size(). Place the type sanity at the last, becase there will be soon an impl level get_viommu_size op, which will require the same sanity tests prior. It can simply insert a piece of code in front of the IOMMU_VIOMMU_TYPE_ARM_SMMUV3 sanity. The core will ensure the viommu_type is set to the core vIOMMU object, and pass in the same dev pointer, so arm_vsmmu_init() won't need to repeat the same sanity tests but to simply init the arm_vsmmu struct. Remove the arm_vsmmu_alloc, completing the replacement. Signed-off-by: Nicolin Chen Acked-by: Will Deacon Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 11 +++-- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 46 ++++++++++--------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +- 3 files changed, 32 insertions(+), 28 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ea41d790463e..bb39af84e6b0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1034,18 +1034,19 @@ struct arm_vsmmu { =20 #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type); -struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, - struct iommu_domain *parent, - struct iommufd_ctx *ictx, - unsigned int viommu_type); +size_t arm_smmu_get_viommu_size(struct device *dev, + enum iommu_viommu_type viommu_type); +int arm_vsmmu_init(struct iommufd_viommu *viommu, + struct iommu_domain *parent_domain); int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, struct arm_smmu_nested_domain *nested_domain); void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master); int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); #else +#define arm_smmu_get_viommu_size NULL #define arm_smmu_hw_info NULL -#define arm_vsmmu_alloc NULL +#define arm_vsmmu_init NULL =20 static inline int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index e4fd8d522af8..9f59c95a254c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -382,25 +382,14 @@ static const struct iommufd_viommu_ops arm_vsmmu_ops = =3D { .cache_invalidate =3D arm_vsmmu_cache_invalidate, }; =20 -struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, - struct iommu_domain *parent, - struct iommufd_ctx *ictx, - unsigned int viommu_type) +size_t arm_smmu_get_viommu_size(struct device *dev, + enum iommu_viommu_type viommu_type) { - struct arm_smmu_device *smmu =3D - iommu_get_iommu_dev(dev, struct arm_smmu_device, iommu); struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); - struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent); - struct arm_vsmmu *vsmmu; - - if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) - return ERR_PTR(-EOPNOTSUPP); + struct arm_smmu_device *smmu =3D master->smmu; =20 if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) - return ERR_PTR(-EOPNOTSUPP); - - if (s2_parent->smmu !=3D master->smmu) - return ERR_PTR(-EINVAL); + return 0; =20 /* * FORCE_SYNC is not set with FEAT_NESTING. Some study of the exact HW @@ -408,7 +397,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *d= ev, * any change to remove this. */ if (WARN_ON(smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) - return ERR_PTR(-EOPNOTSUPP); + return 0; =20 /* * Must support some way to prevent the VM from bypassing the cache @@ -420,19 +409,32 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device = *dev, */ if (!arm_smmu_master_canwbs(master) && !(smmu->features & ARM_SMMU_FEAT_S2FWB)) - return ERR_PTR(-EOPNOTSUPP); + return 0; =20 - vsmmu =3D iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, - &arm_vsmmu_ops); - if (IS_ERR(vsmmu)) - return ERR_CAST(vsmmu); + if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return 0; + + return VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); +} + +int arm_vsmmu_init(struct iommufd_viommu *viommu, + struct iommu_domain *parent_domain) +{ + struct arm_vsmmu *vsmmu =3D container_of(viommu, struct arm_vsmmu, core); + struct arm_smmu_device *smmu =3D + container_of(viommu->iommu_dev, struct arm_smmu_device, iommu); + struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent_domain); + + if (s2_parent->smmu !=3D smmu) + return -EINVAL; =20 vsmmu->smmu =3D smmu; vsmmu->s2_parent =3D s2_parent; /* FIXME Move VMID allocation from the S2 domain allocation to here */ vsmmu->vmid =3D s2_parent->s2_cfg.vmid; =20 - return &vsmmu->core; + viommu->ops =3D &arm_vsmmu_ops; + return 0; } =20 int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 10cc6dc26b7b..181d07bc1a9d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3688,7 +3688,8 @@ static struct iommu_ops arm_smmu_ops =3D { .get_resv_regions =3D arm_smmu_get_resv_regions, .page_response =3D arm_smmu_page_response, .def_domain_type =3D arm_smmu_def_domain_type, - .viommu_alloc =3D arm_vsmmu_alloc, + .get_viommu_size =3D arm_smmu_get_viommu_size, + .viommu_init =3D arm_vsmmu_init, .user_pasid_table =3D 1, .pgsize_bitmap =3D -1UL, /* Restricted during device attach */ .owner =3D THIS_MODULE, --=20 2.43.0