From nobody Thu Sep 11 16:27:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BA3BC6379F for ; Sat, 18 Feb 2023 02:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229632AbjBRCTQ (ORCPT ); Fri, 17 Feb 2023 21:19:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229771AbjBRCTH (ORCPT ); Fri, 17 Feb 2023 21:19:07 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BEB86CA1E; Fri, 17 Feb 2023 18:19:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676686745; x=1708222745; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BUBUA7scA36Z4hLce+dI5gx68bfpdeZbVZePee9ws8o=; b=aYQK+hcxs3UgJRhb5wJNlxJavb1QsYg7GGmIZPzraUKo/RwwCVV4e3Jp i0wLrNNDoMN/wVJaNuAC14lAppYehSflEkIFRFZPv+5+mgPHYxFh3ZqMc 9BLfYwHlx+VYXzP2bS8Wt7iBh97w0HBeDobmkriTuuWEzravwk0Y7ThB9 ICiSuby5H97pJQAn17uHukWmWQ4uwMDbs+lLrOpsAlkY1sskgOq2NP0NM JcOvODzjym55CtwUW0toxUbVbe2yZPTu7uLEuatUM9MONg9GhnSejLyV9 Cs8GvItTcHBnlxLDx0XdltERJrxcbN9Qi9SwliEIoGcUfA3GhXrwlYsdn Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10624"; a="320244226" X-IronPort-AV: E=Sophos;i="5.97,306,1669104000"; d="scan'208";a="320244226" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2023 18:19:04 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10624"; a="672787896" X-IronPort-AV: E=Sophos;i="5.97,306,1669104000"; d="scan'208";a="672787896" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.252.133.15]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Feb 2023 18:19:04 -0800 From: alison.schofield@intel.com To: Dan Williams , Ira Weiny , Vishal Verma , Dave Jiang , Ben Widawsky , Steven Rostedt Cc: Alison Schofield , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron Subject: [PATCH v7 5/6] cxl/trace: Add an HPA to cxl_poison trace events Date: Fri, 17 Feb 2023 18:18:53 -0800 Message-Id: <63760e08571361e4aa418dab3005a008fee0df60.1676685180.git.alison.schofield@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alison Schofield When a cxl_poison trace event is reported for a region, the poisoned Device Physical Address (DPA) can be translated to a Host Physical Address (HPA) for consumption by user space. Translate and add the resulting HPA to the cxl_poison trace event. Follow the device decode logic as defined in the CXL Spec 3.0 Section 8.2.4.19.13. If no region currently maps the poison, assign ULLONG_MAX to the cxl_poison event hpa field. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Alison Schofield --- drivers/cxl/core/trace.c | 94 ++++++++++++++++++++++++++++++++++++++++ drivers/cxl/core/trace.h | 9 +++- 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/trace.c b/drivers/cxl/core/trace.c index 29ae7ce81dc5..d0403dc3c8ab 100644 --- a/drivers/cxl/core/trace.c +++ b/drivers/cxl/core/trace.c @@ -1,5 +1,99 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ =20 +#include +#include "core.h" + #define CREATE_TRACE_POINTS #include "trace.h" + +static bool cxl_is_hpa_in_range(u64 hpa, struct cxl_region *cxlr, int pos) +{ + struct cxl_region_params *p =3D &cxlr->params; + int gran =3D p->interleave_granularity; + int ways =3D p->interleave_ways; + u64 offset; + + /* Is the hpa within this region at all */ + if (hpa < p->res->start || hpa > p->res->end) { + dev_dbg(&cxlr->dev, + "Addr trans fail: hpa 0x%llx not in region\n", hpa); + return false; + } + + /* Is the hpa in an expected chunk for its pos(-ition) */ + offset =3D hpa - p->res->start; + offset =3D do_div(offset, gran * ways); + if ((offset >=3D pos * gran) && (offset < (pos + 1) * gran)) + return true; + + dev_dbg(&cxlr->dev, + "Addr trans fail: hpa 0x%llx not in expected chunk\n", hpa); + + return false; +} + +static u64 cxl_dpa_to_hpa(u64 dpa, struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled) +{ + u64 dpa_offset, hpa_offset, bits_upper, mask_upper, hpa; + struct cxl_region_params *p =3D &cxlr->params; + int pos =3D cxled->pos; + u16 eig =3D 0; + u8 eiw =3D 0; + + ways_to_eiw(p->interleave_ways, &eiw); + granularity_to_eig(p->interleave_granularity, &eig); + + /* + * The device position in the region interleave set was removed + * from the offset at HPA->DPA translation. To reconstruct the + * HPA, place the 'pos' in the offset. + * + * The placement of 'pos' in the HPA is determined by interleave + * ways and granularity and is defined in the CXL Spec 3.0 Section + * 8.2.4.19.13 Implementation Note: Device Decode Logic + */ + + /* Remove the dpa base */ + dpa_offset =3D dpa - cxl_dpa_resource_start(cxled); + + mask_upper =3D GENMASK_ULL(51, eig + 8); + + if (eiw < 8) { + hpa_offset =3D (dpa_offset & mask_upper) << eiw; + hpa_offset |=3D pos << (eig + 8); + } else { + bits_upper =3D (dpa_offset & mask_upper) >> (eig + 8); + bits_upper =3D bits_upper * 3; + hpa_offset =3D ((bits_upper << (eiw - 8)) + pos) << (eig + 8); + } + + /* The lower bits remain unchanged */ + hpa_offset |=3D dpa_offset & GENMASK_ULL(eig + 7, 0); + + /* Apply the hpa_offset to the region base address */ + hpa =3D hpa_offset + p->res->start; + + if (!cxl_is_hpa_in_range(hpa, cxlr, cxled->pos)) + return ULLONG_MAX; + + return hpa; +} + +u64 cxl_trace_hpa(struct cxl_region *cxlr, struct cxl_memdev *cxlmd, + u64 dpa) +{ + struct cxl_region_params *p =3D &cxlr->params; + struct cxl_endpoint_decoder *cxled =3D NULL; + + for (int i =3D 0; i < p->nr_targets; i++) { + cxled =3D p->targets[i]; + if (cxlmd =3D=3D cxled_to_memdev(cxled)) + break; + } + if (!cxled || cxlmd !=3D cxled_to_memdev(cxled)) + return ULLONG_MAX; + + return cxl_dpa_to_hpa(dpa, cxlr, cxled); +} diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index 289fab1a686d..3604f31df7a6 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -612,6 +612,8 @@ TRACE_EVENT(cxl_memory_module, #define cxl_poison_overflow(flags, time) \ (flags & CXL_POISON_FLAG_OVERFLOW ? le64_to_cpu(time) : 0) =20 +u64 cxl_trace_hpa(struct cxl_region *cxlr, struct cxl_memdev *memdev, u64 = dpa); + TRACE_EVENT(cxl_poison, =20 TP_PROTO(struct cxl_memdev *cxlmd, struct cxl_region *region, @@ -626,6 +628,7 @@ TRACE_EVENT(cxl_poison, __field(u64, serial) __string(region, region) __field(u64, overflow_t) + __field(u64, hpa) __field(u64, dpa) __field(u32, length) __array(char, uuid, 16) @@ -645,18 +648,22 @@ TRACE_EVENT(cxl_poison, if (region) { __assign_str(region, dev_name(®ion->dev)); memcpy(__entry->uuid, ®ion->params.uuid, 16); + __entry->hpa =3D cxl_trace_hpa(region, cxlmd, + __entry->dpa); } else { __assign_str(region, ""); memset(__entry->uuid, 0, 16); + __entry->hpa =3D ULLONG_MAX; } ), =20 - TP_printk("memdev=3D%s host=3D%s serial=3D%lld region=3D%s region_uuid=3D= %pU dpa=3D0x%llx length=3D0x%x source=3D%s flags=3D%s overflow_time=3D%llu", + TP_printk("memdev=3D%s host=3D%s serial=3D%lld region=3D%s region_uuid=3D= %pU hpa=3D0x%llx dpa=3D0x%llx length=3D0x%x source=3D%s flags=3D%s overflow= _time=3D%llu", __get_str(memdev), __get_str(host), __entry->serial, __get_str(region), __entry->uuid, + __entry->hpa, __entry->dpa, __entry->length, show_poison_source(__entry->source), --=20 2.37.3