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Sun, 12 Oct 2025 16:57:48 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 1/6] iommu: Generic support for RMRs during device release Date: Sun, 12 Oct 2025 16:57:37 -0700 Message-ID: <631ef0483b8d1981d037131d0f342c6970ffc155.1760312540.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|SJ1PR12MB6219:EE_ X-MS-Office365-Filtering-Correlation-Id: 949994c1-c008-4e19-bea1-08de09eb2b00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OVndwf61hCayzo9konwB9wH1Vw2u6HWwBOgvsd0u+kLr2G/AwVBhdd2gZsrU?= =?us-ascii?Q?rBhk0kIn4Iaw3y+pQHGOKLTaMqb9BpHS1hXfCHBMz//N5Cgk360UAQZmkX2D?= =?us-ascii?Q?CpyAaG49Fjam/pRa3AsdJ49RNVjmqQrKSihRsnzPknqxQr/hymgx7KsawcFC?= =?us-ascii?Q?xbrUTZRGenAqPwyCtEiCxnEuX8ZZQWC1nYgUtAGEbcQrgzKbZ/rTEe+sxJ+A?= =?us-ascii?Q?AanARun6DAci9qGoXvciuZ7kyiuTp5s51XPizqfDZuOVvs2kuc5GBnB4KvsF?= =?us-ascii?Q?pVU8DbOkNHVrKHJ3hli9ksR7E1hHZCEAjqN5uc/+adZUVEJM+yGERYB2j9VS?= =?us-ascii?Q?Xj9JzXPF5d0NIqpwEo0swEz5j+XUm2VUsVP0UZmBZaTVQSyojuEYTY2/Lxp8?= =?us-ascii?Q?ruztFFEkOtlu4+HR4KMyps89r9SeAJ5ZvDnSAtumA7jDFRqD3I27LsbmLqOA?= =?us-ascii?Q?Q07xYWh0ZVjP0CNS6RkKz1i9PchqlaEPFHk7kroFfHiRhdt5I1SPsEQXJu/I?= =?us-ascii?Q?U6KYW/Wl6Sg9wkMxAClD3uopVA4KIY8uk5HsF21H9KaFEXXxrdf491Co4KWR?= =?us-ascii?Q?VCIvdqQKPi8dJ1hhzDhiLBd2x8M4BcnTZQAdl0iNBLWFk1ceMD8+ODcNJriF?= =?us-ascii?Q?6Cmrr946MhXng7GM+RxNeQUJGWSRWSppvLWUr5DXGkjFs+zDzSdVOaRR5Eb8?= =?us-ascii?Q?ubCYfPJfTV+x4gDVMej/r0wjSZEnHlv5MDOSQJYVVPer2VkCEN7RTM95EsN6?= =?us-ascii?Q?3hvuYt84x3Qy9FZWqULqOuphPAEalIj3T4Rc6ITOI2Jm6I5AzDzSX68V1C2U?= =?us-ascii?Q?RNYESnwB8Cyk7KruW1vNad6Tj2KfB/cWns2CuS8CAAi1kUaxITR8bSQMkMA4?= =?us-ascii?Q?unlHo7BYrPTcKVUpmkdOs8qWSYOSiMTMU1atnvh/m0tmfzl8cAdSc6JRwN0Q?= =?us-ascii?Q?l4/effomLjYj98sy7Yv50tV7yjhZ9j/oM4O9RwKyvPjxNARZ35sgopRa6lS9?= =?us-ascii?Q?gtombJAXllvnf5/1nZvBDPyTwP8HT1Kw2V0Fmp2AYiJ+zpeRsOJ0TfNzntp/?= =?us-ascii?Q?yMbGPIGCu+KdkS6ZvbU1t8dSKMTEXqlBVB7XtZAELNfQOXT4tt+DKCgT7cNt?= =?us-ascii?Q?kR9gseQctbyBm3D5vNhSO6sQfM1tgpYpel9CGi9xfMYQSGOlPDGPanctZhaT?= =?us-ascii?Q?BAx6zD8Rio8GXJtLbl4/xn1v4X2mdJvd8GRJr9pQ0+AwOWptW+fd5tYGxyOp?= =?us-ascii?Q?Z9raF/NmcMLVtKOipJK+k8bzammfPdODQwhzHLxFOhAPPl+Oa3dRi/KQ48CC?= =?us-ascii?Q?x6mRLvOy+BFNKsHgYEySTX5B9A9o0RMkReCFCFW4Hp/r2HrKxU65QVbg138R?= =?us-ascii?Q?x7fGapS9r64PnVWixn+Yk6KlYPDh8DHVtgZRtr5UpkS/HWsTF0iipQfkrAGB?= =?us-ascii?Q?T4qKkTNIrA3D9JLGtDV8nwwA9JLgDmHxLbVFQJgQo41JpCLpZWK1ARsXC0Cf?= =?us-ascii?Q?z3L3/XLgmtg6OYCbYFA52uMKsLxiLmYboTTPeBn9oOwMZaiLCgtQvA4nmHYT?= =?us-ascii?Q?ncebb/BvnYPa+BESmtU=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2025 23:57:57.5266 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 949994c1-c008-4e19-bea1-08de09eb2b00 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6219 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Generally an IOMMU driver should leave the translation as BLOCKED until the translation entry is probed onto a struct device. When the struct device is removed, the translation should be put back to BLOCKED. Drivers that are able to work like this can set their release_domain to the blocking domain, and the core code handles this work. The exception is when the device has an IOMMU_RESV_DIRECT region, in which case the OS should continuously allow translations for the given range. And the core code generally prevents using a BLOCKED domain with this device. Continue this logic for the device release and hoist some open coding from drivers. If the device has dev->iommu->require_direct and the driver uses a BLOCKED release_domain, override it to IDENTITY to preserve the semantics. The only remaining required driver code for IOMMU_RESV_DIRECT should preset an IDENTITY translation during early IOMMU startup for those devices. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 59244c744eabd..adef1a37f9311 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -542,8 +542,20 @@ static void iommu_deinit_device(struct device *dev) * Regardless, if a delayed attach never occurred, then the release * should still avoid touching any hardware configuration either. */ - if (!dev->iommu->attach_deferred && ops->release_domain) - ops->release_domain->ops->attach_dev(ops->release_domain, dev); + if (!dev->iommu->attach_deferred && ops->release_domain) { + struct iommu_domain *release_domain =3D ops->release_domain; + + /* + * If the device requires direct mappings then it should not + * be parked on a BLOCKED domain during release as that would + * break the direct mappings. + */ + if (dev->iommu->require_direct && ops->identity_domain && + release_domain =3D=3D ops->blocked_domain) + release_domain =3D ops->identity_domain; + + release_domain->ops->attach_dev(release_domain, dev); + } =20 if (ops->release_device) ops->release_device(dev); --=20 2.43.0