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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org Subject: [PATCH 1/4] net: stmmac: s32: use the syscon interface PHY_INTF_SEL_RGMII Message-ID: <6275e666a7ef78bd4c758d3f7f6fb6f30407393e.1764592300.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the s32 chipset the GMAC_0_CTRL_STS register is in GPR region. Originally, accessing this register was done in a sort of ad-hoc way, but we want to use the syscon interface to do it. This is a little bit uglier because we to maintain backwards compatibility to the old device trees so we have to support both ways to access this register. Signed-off-by: Dan Carpenter --- .../net/ethernet/stmicro/stmmac/dwmac-s32.c | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index 5a485ee98fa7..20de761b7d28 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include =20 #include "stmmac_platform.h" @@ -32,6 +34,8 @@ struct s32_priv_data { void __iomem *ioaddr; void __iomem *ctrl_sts; + struct regmap *sts_regmap; + unsigned int sts_offset; struct device *dev; phy_interface_t *intf_mode; struct clk *tx_clk; @@ -40,7 +44,10 @@ struct s32_priv_data { =20 static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) { - writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + if (gmac->ctrl_sts) + writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + else + regmap_write(gmac->sts_regmap, gmac->sts_offset, PHY_INTF_SEL_RGMII); =20 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); =20 @@ -125,10 +132,16 @@ static int s32_dwmac_probe(struct platform_device *pd= ev) "dt configuration failed\n"); =20 /* PHY interface mode control reg */ - gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(gmac->ctrl_sts)) - return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), - "S32CC config region is missing\n"); + gmac->sts_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "phy-sel", 1, &gmac->sts_offset); + if (gmac->sts_regmap =3D=3D ERR_PTR(-EPROBE_DEFER)) + return PTR_ERR(gmac->sts_regmap); + if (IS_ERR(gmac->sts_regmap)) { + gmac->ctrl_sts =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(gmac->ctrl_sts)) + return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts), + "S32CC config region is missing\n"); + } =20 /* tx clock */ gmac->tx_clk =3D devm_clk_get(&pdev->dev, "tx"); --=20 2.51.0