From nobody Fri Sep 19 05:08:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B82BC4167B for ; Thu, 8 Dec 2022 23:36:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230144AbiLHXgE (ORCPT ); Thu, 8 Dec 2022 18:36:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230041AbiLHXfy (ORCPT ); Thu, 8 Dec 2022 18:35:54 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E50E6BC9E; Thu, 8 Dec 2022 15:35:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670542553; x=1702078553; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hqWWs96g8j8J+o2BvB4eR8w2w9BH0DQPRuS3KFwmOI0=; b=OJFsnkFcBEWPqqI9NfmohL47IGuhyowHDLgLDBd2cb9RvLBciEEypIOO wx0ahMX2Wl6CGukf5R229FizILWDiwoIzVCo7kIrSwJ8DIeGS8OklDfNy BUUNp2kEHrUNxCpf1eB3Vc//1FRuupwPUXd2BPLNiqHtj9dly/XAhpOBa xJpQsYnBKMZu2Ya42fkTVEuKsr/A3VD+C1nIYXLSwvra8V+n2hEojcBTC vWylfUCXkc/AO59/PBuEl1qDRo4UkPRLBmRhRmferLtM64GXlGd6rWRX4 /QRS+2JFtlfvslpNthEEBuMdoK/F/uhyHmqIcYofhK1lcRbBydWFz3NZq A==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="403586481" X-IronPort-AV: E=Sophos;i="5.96,228,1665471600"; d="scan'208";a="403586481" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 15:35:52 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="677950888" X-IronPort-AV: E=Sophos;i="5.96,228,1665471600"; d="scan'208";a="677950888" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 15:35:52 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , Sean Christopherson , David Matlack Subject: [RFC PATCH v2 02/15] KVM: TDX: Pass page level to cache flush before TDX SEAMCALL Date: Thu, 8 Dec 2022 15:35:37 -0800 Message-Id: <6134a82d4a78d5a7aee4d684d7d4dab34f7f1bcf.1670541736.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li tdh_mem_page_aug() will support 2MB large page in the near future. Cache flush also needs to be 2MB instead of 4KB in such cases. Introduce a helper function to flush cache with page size info in preparation for large pages. Signed-off-by: Xiaoyao Li Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/tdx_ops.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/vmx/tdx_ops.h b/arch/x86/kvm/vmx/tdx_ops.h index 86330d0e4b22..4db983b1dc94 100644 --- a/arch/x86/kvm/vmx/tdx_ops.h +++ b/arch/x86/kvm/vmx/tdx_ops.h @@ -6,6 +6,7 @@ =20 #include =20 +#include #include #include #include @@ -18,6 +19,11 @@ =20 void pr_tdx_error(u64 op, u64 error_code, const struct tdx_module_output *= out); =20 +static inline void tdx_clflush_page(hpa_t addr, enum pg_level level) +{ + clflush_cache_range(__va(addr), KVM_HPAGE_SIZE(level)); +} + /* * TDX module acquires its internal lock for resources. It doesn't spin t= o get * locks because of its restrictions of allowed execution time. Instead, = it @@ -50,21 +56,21 @@ static inline u64 seamcall_sept(u64 op, u64 rcx, u64 rd= x, u64 r8, u64 r9, =20 static inline u64 tdh_mng_addcx(hpa_t tdr, hpa_t addr) { - clflush_cache_range(__va(addr), PAGE_SIZE); + tdx_clflush_page(addr, PG_LEVEL_4K); return __seamcall(TDH_MNG_ADDCX, addr, tdr, 0, 0, NULL); } =20 static inline u64 tdh_mem_page_add(hpa_t tdr, gpa_t gpa, hpa_t hpa, hpa_t = source, struct tdx_module_output *out) { - clflush_cache_range(__va(hpa), PAGE_SIZE); + tdx_clflush_page(hpa, PG_LEVEL_4K); return seamcall_sept(TDH_MEM_PAGE_ADD, gpa, tdr, hpa, source, out); } =20 static inline u64 tdh_mem_sept_add(hpa_t tdr, gpa_t gpa, int level, hpa_t = page, struct tdx_module_output *out) { - clflush_cache_range(__va(page), PAGE_SIZE); + tdx_clflush_page(page, PG_LEVEL_4K); return seamcall_sept(TDH_MEM_SEPT_ADD, gpa | level, tdr, page, 0, out); } =20 @@ -76,21 +82,21 @@ static inline u64 tdh_mem_sept_remove(hpa_t tdr, gpa_t = gpa, int level, =20 static inline u64 tdh_vp_addcx(hpa_t tdvpr, hpa_t addr) { - clflush_cache_range(__va(addr), PAGE_SIZE); + tdx_clflush_page(addr, PG_LEVEL_4K); return __seamcall(TDH_VP_ADDCX, addr, tdvpr, 0, 0, NULL); } =20 static inline u64 tdh_mem_page_relocate(hpa_t tdr, gpa_t gpa, hpa_t hpa, struct tdx_module_output *out) { - clflush_cache_range(__va(hpa), PAGE_SIZE); + tdx_clflush_page(hpa, PG_LEVEL_4K); return __seamcall(TDH_MEM_PAGE_RELOCATE, gpa, tdr, hpa, 0, out); } =20 static inline u64 tdh_mem_page_aug(hpa_t tdr, gpa_t gpa, hpa_t hpa, struct tdx_module_output *out) { - clflush_cache_range(__va(hpa), PAGE_SIZE); + tdx_clflush_page(hpa, PG_LEVEL_4K); return seamcall_sept(TDH_MEM_PAGE_AUG, gpa, tdr, hpa, 0, out); } =20 @@ -107,13 +113,13 @@ static inline u64 tdh_mng_key_config(hpa_t tdr) =20 static inline u64 tdh_mng_create(hpa_t tdr, int hkid) { - clflush_cache_range(__va(tdr), PAGE_SIZE); + tdx_clflush_page(tdr, PG_LEVEL_4K); return __seamcall(TDH_MNG_CREATE, tdr, hkid, 0, 0, NULL); } =20 static inline u64 tdh_vp_create(hpa_t tdr, hpa_t tdvpr) { - clflush_cache_range(__va(tdvpr), PAGE_SIZE); + tdx_clflush_page(tdvpr, PG_LEVEL_4K); return __seamcall(TDH_VP_CREATE, tdvpr, tdr, 0, 0, NULL); } =20 --=20 2.25.1