From nobody Sat Feb 7 11:38:07 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010042.outbound.protection.outlook.com [52.101.193.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFE13364E9D for ; Tue, 27 Jan 2026 18:55:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.193.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769540148; cv=fail; b=S/vlVxdGqTbP6CokCQnhUhyjax9aIj1HDOWhYdrWL8+VwSsSc3NMEsfz7W3dKNpD/gscHCK0aKozmE6hSW1FN3opeU7oxNTRJ+q+qrvRmnIW3NFB6qYIdwaWqdWGqt73SRxlQEeKWKv0fkhAHEnsJC/42wtTQmRrW4VpM45LsEE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769540148; c=relaxed/simple; bh=NwSl04VkX+HdeZ3E/guXZ+NETx6+PsPxw1aBNmqG6qE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fy7ow85U3hxfF+H3Ioe7klKh51Cd3TE629R+s/PoM2xTHbu+rhSldFqxlQ9dBTUI70wH/eFf/FPlRZYC/ttM+VWA/4SG1QkCTyepvUKna2TICUmg6G7DWA+y66tHkQTQGX57kvWkK16T4/8ZAJk3y0C6FO8TgJ+Jhu80Ajo0/G8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=CptsnFKw; arc=fail smtp.client-ip=52.101.193.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CptsnFKw" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nPqcgSM8/mtjgA3drPCOr5KRbBjmQdu19xepzUY9DNdlXqru9RJUzesHog1Rn685L6BLFJtyGg5oSNs2lJSv1hgh/9yTHTG8v5PRMQ9UdMjWDSKAE7dA63EjI8lw2DVM1zgRPL0Fkjwn8E/ko1X1aao1LxXaCV4RlSP5WD60jlzQxmI84spsLMxyV4Gy/GW6HN6WbyPteUBRokzcLqBNnrEbKm5K/JLMFmNzYP1tkPKBvCf5PoE77dffT+01NkGDJBslFvBX6mBRfnNaqt00Br/FhSUmNfATVcMILOQJ/6XDJ1GjlhS36ANEW8MqKKWnjJh/jDG1XmTdz2hT6/qWBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=02Rwyd1L2TMl8CMh9HzPGyLxKB/rBKO0E/qtKyXK5LA=; b=GQH2MzpTPeeMrMljckx0RP7fdhx8ia7vyJPXZtpHRTxNBUdUldtBm6Rip2oLUWAq200JuncLWwgBYN1jsJ84yB1Vrx3kaT7X6rvYb3i8ZtRQtaiUF1ED2vjLAtQGJynUfQ3Mq+emCIjhuY8s+TWwJgPixUSP1yynng2zFkSzhBAXCjxEcTMiK81yA8Nx2FGJ/ZYt0CDleeUtnpr9UQPqPzDvHnziBR0GbQIquF4cC11640syQsUX3QdwlsxDNaUfy8xcdJTd0i0r9+X9zzq4bWGo1Oxf1RHWsZm8KFbFDRoSs3IOOSBd/I0CQSia7IQncofPURsnRFcXYT7clqJbww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=02Rwyd1L2TMl8CMh9HzPGyLxKB/rBKO0E/qtKyXK5LA=; b=CptsnFKwmnryfMP93gfX/NH9J+nunKZi/xzVtSh4h+nqoeIJXYBdkiumSF62HzKSvg/mUCU28KXmToh4QFWCYifByB0a55no7L6+JdR+UeKH1TD+iD5uEds7yoR4vQ9IzbCRTffbLbLorobkuZwzljyuY9ykTuIN641ihJjgouZnWUyK+dRuzcb8gojSAgWesn7eMOl9/Dt1eesEHSiu9ORRxnyq1ejOIPfDXrLFRE7FplJOo0AICgYawv35IahQRYkf3X0ylcSicZyovl68pPCrII1C7QUNVbCiFYKNqdDIN73bHd+LbLVjOEA64BlCyM/5ddjY4jJBf2KQCaeAGA== Received: from SJ0PR03CA0175.namprd03.prod.outlook.com (2603:10b6:a03:338::30) by DS0PR12MB8477.namprd12.prod.outlook.com (2603:10b6:8:15b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.16; Tue, 27 Jan 2026 18:55:37 +0000 Received: from SJ1PEPF00002320.namprd03.prod.outlook.com (2603:10b6:a03:338:cafe::9) by SJ0PR03CA0175.outlook.office365.com (2603:10b6:a03:338::30) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.16 via Frontend Transport; Tue, 27 Jan 2026 18:55:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00002320.mail.protection.outlook.com (10.167.242.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Tue, 27 Jan 2026 18:55:37 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 27 Jan 2026 10:55:15 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 27 Jan 2026 10:55:15 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 27 Jan 2026 10:55:14 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v11 8/8] iommu/arm-smmu-v3: Perform per-domain invalidations using arm_smmu_invs Date: Tue, 27 Jan 2026 10:55:00 -0800 Message-ID: <60cd04895075d1f2046f394fdfdae9e7b8d79b3e.1769539310.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002320:EE_|DS0PR12MB8477:EE_ X-MS-Office365-Filtering-Correlation-Id: d2011444-fabf-448e-42b9-08de5dd5a8cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?L6SRKuI8fn44nt30Hu3i454wiHv6FpFFP2YpqYlm3QuzDm6Jw1IdYM4W8ZDa?= =?us-ascii?Q?nLklLRLLRc283qCKaT09CPhPQMbEUarIOhMjogpV+tSJitsbxQEbhrrCctRg?= =?us-ascii?Q?GuSoLbeddqx1+nUfHn7OuGMXPClPe6WKTPVZXI2HxYD8vQ4WDvpKL/Ro2828?= =?us-ascii?Q?XcjxwSs3qPo2skWKVmD6rA4hBlvKoy/n8jxf8p6JBwXUpkxw99aXyVXJK8mK?= =?us-ascii?Q?+kMd+P7mW5cpp7xYg7ZHN8JN6bHdoYKvqb6JNrSlP7n5QGsuJ62s7Mlne+vr?= =?us-ascii?Q?gORZF0RrrDQC17jzn3hi3NUvrFmc39aevz0vorpFlSSDgKCWNebwOHx1K7FK?= =?us-ascii?Q?DELqUdZMO+zx1EGCBZMH3iDcVGmnLQ1GPdZxk2xL18hqXeOfhq937DbOlbeh?= =?us-ascii?Q?Ln5YVFvr3lhwLAIEn5Qv6iv+oKou9bqp+0EdDeBjq5fgAy+JlVH1WlKdcDpk?= =?us-ascii?Q?Wt8S1ay/SlfEq9EEdo2+w0YUuAI/xF+aSZqAzGcmVLPQ4aLy0bbbs60Jonaq?= =?us-ascii?Q?gh+wf2O1CHzMN8Wbc+tSYlHy3nmHSywqKr1ZKcJCohYoAMnBTQLWwGwDv2Y0?= =?us-ascii?Q?xHmh2kmWnIWELJdFf4rXaFVQnkcjJTRUCYUqz4uT0iR5tTGJGGnUeTOtvKhx?= =?us-ascii?Q?CkmtLKXWvotZw6UjwwSrK7okbpqs1SLQWQHXjTFyBXElq3EO/osy64O4nGQI?= =?us-ascii?Q?uVA42V7CSXNeGLOw1p8HCcIxvVcbfufs7ZYr+spBO//45mr1ZQQedDfp005n?= =?us-ascii?Q?pbyTf327bt2Tgbp7Us3pn1p6Fc/OfzF25/8F6/Hgx0+VYZslFEO+rPG9eN2W?= =?us-ascii?Q?AyziGdgQyOwjVJ40aWAX8jVR02Mq08LGRWFTWBQUYZE8fpVLKwpO5tv2aJ/g?= =?us-ascii?Q?P7uq9qQGH2MuV8y0yVQAJnI1d/pFbDi5Qm/4aM+3hJXanZXRk7MqSBOw66Wt?= =?us-ascii?Q?9kcVjgRc/VYAEngnPOcJwXb0upvEo/m/aJRgjjhcHQu1msUyhpZe1mxEZTYt?= =?us-ascii?Q?xJGoGHOZQQ8rAaSkIKMtJct01UdD1LTpJUig5NNIwCYo+SExPlqab+CZWR0D?= =?us-ascii?Q?EyrStTWS80pAeMknbocSpnDXARbiv44fjgWWA+Z9kCS38l7unnC+DuqKCa7v?= =?us-ascii?Q?NIqAiyNGYme24viJzGhWcto3rt76F/pK2h8e5wlJwp7zcaySrWcYWKyn0FJi?= =?us-ascii?Q?a8jXjPlh0manMwG6NG9aPKbnfKnX1AaMWXIICZi515jU8hAHxyLUz7RNm3to?= =?us-ascii?Q?CuKtAZ8Ai8L5Q2xwyW+h30aMFj2x56YTE4EDdhvOvKYGf4KL2GkSYSutZtUS?= =?us-ascii?Q?JYO9hM7CqUXP3rtXl8lQxlIu5bI5CC28xaclHVhAu6I9t5BqrBMiTgqdqoiq?= =?us-ascii?Q?upeJN/Et6TtsVvAHIW1dqunLH3qgb52L4vrwMlBQWLDdglySN5PHZbLQK0gA?= =?us-ascii?Q?0fJ2gn3PTrxFnEUKhMJU8eoWJLlgPPahChoj8jOAPh7iIG6kbz7B+al3fRkj?= =?us-ascii?Q?c5hX7pd0G3xoNHZ54U+sRkEV+2J0F/WY3vFqOfF+USy7Gk48nEIdqamtOL/U?= =?us-ascii?Q?kUyjOGEFJLH9DUkmVuik6jWkzt+utsyhQlhkuj8kKJcePfsNioHJoGT48IOD?= =?us-ascii?Q?dMRQLOLjnfEPvsJEqNf76E25H55zQLxIHSz0lxr4zd5zQ6j9HK+caE7RcS14?= =?us-ascii?Q?6SHDgg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2026 18:55:37.4144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2011444-fabf-448e-42b9-08de5dd5a8cb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002320.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8477 Content-Type: text/plain; charset="utf-8" Replace the old invalidation functions with arm_smmu_domain_inv_range() in all the existing invalidation routines. And deprecate the old functions. The new arm_smmu_domain_inv_range() handles the CMDQ_MAX_TLBI_OPS as well, so drop it in the SVA function. Since arm_smmu_cmdq_batch_add_range() has only one caller now, and it must be given a valid size, add a WARN_ON_ONCE to catch any missed case. Also update the comments in arm_smmu_tlb_inv_context() to clarify things with the new invalidation functions. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 - .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 29 +-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 183 ++---------------- 3 files changed, 24 insertions(+), 195 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 534e9a5ddca3..36de2b0b2ebe 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1080,13 +1080,6 @@ int arm_smmu_set_pasid(struct arm_smmu_master *maste= r, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, struct arm_smmu_cd *cd, struct iommu_domain *old); =20 -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain); -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size); - void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size, unsigned int granule, bool leaf); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 440ad8cc07de..f1f8e01a7e91 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -122,15 +122,6 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_sva_cd); =20 -/* - * Cloned from the MAX_TLBI_OPS in arch/arm64/include/asm/tlbflush.h, this - * is used as a threshold to replace per-page TLBI commands to issue in the - * command queue with an address-space TLBI command, when SMMU w/o a range - * invalidation feature handles too many per-page TLBI commands, which will - * otherwise result in a soft lockup. - */ -#define CMDQ_MAX_TLBI_OPS (1 << (PAGE_SHIFT - 3)) - static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier= *mn, struct mm_struct *mm, unsigned long start, @@ -146,21 +137,8 @@ static void arm_smmu_mm_arch_invalidate_secondary_tlbs= (struct mmu_notifier *mn, * range. So do a simple translation here by calculating size correctly. */ size =3D end - start; - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { - if (size >=3D CMDQ_MAX_TLBI_OPS * PAGE_SIZE) - size =3D 0; - } else { - if (size =3D=3D ULONG_MAX) - size =3D 0; - } - - if (!size) - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - else - arm_smmu_tlb_inv_range_asid(start, size, smmu_domain->cd.asid, - PAGE_SIZE, false, smmu_domain); =20 - arm_smmu_atc_inv_domain(smmu_domain, start, size); + arm_smmu_domain_inv_range(smmu_domain, start, size, PAGE_SIZE, false); } =20 static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct = *mm) @@ -191,8 +169,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) } spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) @@ -302,7 +279,7 @@ static void arm_smmu_sva_domain_free(struct iommu_domai= n *domain) /* * Ensure the ASID is empty in the iommu cache before allowing reuse. */ - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); + arm_smmu_domain_inv(smmu_domain); =20 /* * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index b9db98c793a7..d28bcaeb2113 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1284,16 +1284,6 @@ struct arm_smmu_invs *arm_smmu_invs_purge(struct arm= _smmu_invs *invs) EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_purge); =20 /* Context descriptor manipulation functions */ -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_ASID : CMDQ_OP_TLBI_NH_ASID, - .tlbi.asid =3D asid, - }; - - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); -} =20 /* * Based on the value of ent report which bits of the STE the HW will acce= ss. It @@ -2505,90 +2495,27 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_= master *master, return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); } =20 -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size) -{ - struct arm_smmu_master_domain *master_domain; - int i; - unsigned long flags; - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D CMDQ_OP_ATC_INV, - }; - struct arm_smmu_cmdq_batch cmds; - - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) - return 0; - - /* - * Ensure that we've completed prior invalidation of the main TLBs - * before we read 'nr_ats_masters' in case of a concurrent call to - * arm_smmu_enable_ats(): - * - * // unmap() // arm_smmu_enable_ats() - * TLBI+SYNC atomic_inc(&nr_ats_masters); - * smp_mb(); [...] - * atomic_read(&nr_ats_masters); pci_enable_ats() // writel() - * - * Ensures that we always see the incremented 'nr_ats_masters' count if - * ATS was enabled at the PCI device before completion of the TLBI. - */ - smp_mb(); - if (!atomic_read(&smmu_domain->nr_ats_masters)) - return 0; - - arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd); - - spin_lock_irqsave(&smmu_domain->devices_lock, flags); - list_for_each_entry(master_domain, &smmu_domain->devices, - devices_elm) { - struct arm_smmu_master *master =3D master_domain->master; - - if (!master->ats_enabled) - continue; - - if (master_domain->nested_ats_flush) { - /* - * If a S2 used as a nesting parent is changed we have - * no option but to completely flush the ATC. - */ - arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); - } else { - arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, - &cmd); - } - - for (i =3D 0; i < master->num_streams; i++) { - cmd.atc.sid =3D master->streams[i].id; - arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); - } - } - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); - - return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); -} - /* IO_PGTABLE API */ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_ent cmd; =20 /* - * NOTE: when io-pgtable is in non-strict mode, we may get here with - * PTEs previously cleared by unmaps on the current CPU not yet visible - * to the SMMU. We are relying on the dma_wmb() implicit during cmd - * insertion to guarantee those are observed before the TLBI. Do be - * careful, 007. + * If the DMA API is running in non-strict mode then another CPU could + * have changed the page table and not invoked any flush op. Instead the + * other CPU will do an atomic_read() and this CPU will have done an + * atomic_write(). That handshake is enough to acquire the page table + * writes from the other CPU. + * + * All command execution has a dma_wmb() to release all the in-memory + * structures written by this CPU, that barrier must also release the + * writes acquired from all the other CPUs too. + * + * There are other barriers and atomics on this path, but the above is + * the essential mechanism for ensuring that HW sees the page table + * writes from another CPU before it executes the IOTLB invalidation. */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); - } - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu, @@ -2600,7 +2527,7 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_= smmu_device *smmu, unsigned long end =3D iova + size, num_pages =3D 0, tg =3D pgsize; size_t inv_range =3D granule; =20 - if (!size) + if (WARN_ON_ONCE(!size)) return; =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { @@ -2655,76 +2582,6 @@ static void arm_smmu_cmdq_batch_add_range(struct arm= _smmu_device *smmu, } } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_batch cmds; - size_t pgsize; - - /* Get the leaf page size */ - pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); - - arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); - arm_smmu_cmdq_batch_add_range(smmu, &cmds, cmd, iova, size, granule, - pgsize); - arm_smmu_cmdq_batch_submit(smmu, &cmds); -} - -static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .tlbi =3D { - .leaf =3D leaf, - }, - }; - - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->cd.asid; - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - } - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); - - if (smmu_domain->nest_parent) { - /* - * When the S2 domain changes all the nested S1 ASIDs have to be - * flushed too. - */ - cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; - arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); - } - - /* - * Unfortunately, this can't be leaf-only since we may have - * zapped an entire table. - */ - arm_smmu_atc_inv_domain(smmu_domain, iova, size); -} - -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA, - .tlbi =3D { - .asid =3D asid, - .leaf =3D leaf, - }, - }; - - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); -} - static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t= size, size_t granule) { @@ -2926,7 +2783,9 @@ static void arm_smmu_tlb_inv_page_nosync(struct iommu= _iotlb_gather *gather, static void arm_smmu_tlb_inv_walk(unsigned long iova, size_t size, size_t granule, void *cookie) { - arm_smmu_tlb_inv_range_domain(iova, size, granule, false, cookie); + struct arm_smmu_domain *smmu_domain =3D cookie; + + arm_smmu_domain_inv_range(smmu_domain, iova, size, granule, false); } =20 static const struct iommu_flush_ops arm_smmu_flush_ops =3D { @@ -4196,9 +4055,9 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *= domain, if (!gather->pgsize) return; =20 - arm_smmu_tlb_inv_range_domain(gather->start, - gather->end - gather->start + 1, - gather->pgsize, true, smmu_domain); + arm_smmu_domain_inv_range(smmu_domain, gather->start, + gather->end - gather->start + 1, + gather->pgsize, true); } =20 static phys_addr_t --=20 2.43.0