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AJvYcCU25EDeKnWim8yl5gHQ5ZXKdWq0xMu4jafr4/63YZDVGGkuHQU/xKKgP7Ofj8R0slX3HB5EReTl/OOEduA=@vger.kernel.org X-Gm-Message-State: AOJu0YzPI8thjx/zDI6zSwIRR4gKVjw1kvMQQcftbU2McFVoHMYYjvQV xzyrliXEBvQlBPcBF+t2aiuhkQ5TT9KigML7OrumFye5AmF/s82dhSXoy0LnEfQ= X-Google-Smtp-Source: AGHT+IElWj3MBVHOh3B+iyij2musyj+SidDkbhoc+Fw3p7WR30V31+IbJsERJ4NjnBhf6uNry2i6AQ== X-Received: by 2002:a17:90a:a00b:b0:2e2:ba35:356c with SMTP id 98e67ed59e1d1-2e2f0dc659emr339295a91.39.1728589713463; Thu, 10 Oct 2024 12:48:33 -0700 (PDT) Received: from tjeznach.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2e6ef1ad0sm749135a91.49.2024.10.10.12.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:48:32 -0700 (PDT) From: Tomasz Jeznach To: Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley Cc: Palmer Dabbelt , Albert Ou , Anup Patel , Sunil V L , Nick Kossifidis , Sebastien Boeuf , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com, Tomasz Jeznach , Lu Baolu Subject: [PATCH v9 3/7] iommu/riscv: Add RISC-V IOMMU PCIe device driver Date: Thu, 10 Oct 2024 12:48:06 -0700 Message-Id: <606ff9e3151cc264bc2377d66508b95619d529b1.1728579958.git.tjeznach@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce device driver for PCIe implementation of RISC-V IOMMU architected hardware. IOMMU hardware and system support for MSI or MSI-X is required by this implementation. Vendor and device identifiers used in this patch matches QEMU implementation of the RISC-V IOMMU PCIe device, from Rivos VID (0x1efd) range allocated by the PCI-SIG. MAINTAINERS | added iommu-pci.c already covered by matching pattern. Link: https://lore.kernel.org/qemu-devel/20240307160319.675044-1-dbarboza@v= entanamicro.com/ Co-developed-by: Nick Kossifidis Signed-off-by: Nick Kossifidis Reviewed-by: Lu Baolu Signed-off-by: Tomasz Jeznach --- drivers/iommu/riscv/Kconfig | 5 ++ drivers/iommu/riscv/Makefile | 1 + drivers/iommu/riscv/iommu-pci.c | 120 ++++++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/iommu/riscv/iommu-pci.c diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig index 5dcc5c45aa50..c071816f59a6 100644 --- a/drivers/iommu/riscv/Kconfig +++ b/drivers/iommu/riscv/Kconfig @@ -13,3 +13,8 @@ config RISCV_IOMMU =20 Say Y here if your SoC includes an IOMMU device implementing the RISC-V IOMMU architecture. + +config RISCV_IOMMU_PCI + def_bool y if RISCV_IOMMU && PCI_MSI + help + Support for the PCIe implementation of RISC-V IOMMU architecture. diff --git a/drivers/iommu/riscv/Makefile b/drivers/iommu/riscv/Makefile index e4c189de58d3..f54c9ed17d41 100644 --- a/drivers/iommu/riscv/Makefile +++ b/drivers/iommu/riscv/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_RISCV_IOMMU) +=3D iommu.o iommu-platform.o +obj-$(CONFIG_RISCV_IOMMU_PCI) +=3D iommu-pci.o diff --git a/drivers/iommu/riscv/iommu-pci.c b/drivers/iommu/riscv/iommu-pc= i.c new file mode 100644 index 000000000000..c7a89143014c --- /dev/null +++ b/drivers/iommu/riscv/iommu-pci.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* + * Copyright =C2=A9 2022-2024 Rivos Inc. + * Copyright =C2=A9 2023 FORTH-ICS/CARV + * + * RISCV IOMMU as a PCIe device + * + * Authors + * Tomasz Jeznach + * Nick Kossifidis + */ + +#include +#include +#include +#include +#include + +#include "iommu-bits.h" +#include "iommu.h" + +/* QEMU RISC-V IOMMU implementation */ +#define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014 + +/* Rivos Inc. assigned PCI Vendor and Device IDs */ +#ifndef PCI_VENDOR_ID_RIVOS +#define PCI_VENDOR_ID_RIVOS 0x1efd +#endif + +#define PCI_DEVICE_ID_RIVOS_RISCV_IOMMU_GA 0x0008 + +static int riscv_iommu_pci_probe(struct pci_dev *pdev, const struct pci_de= vice_id *ent) +{ + struct device *dev =3D &pdev->dev; + struct riscv_iommu_device *iommu; + int rc, vec; + + rc =3D pcim_enable_device(pdev); + if (rc) + return rc; + + if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) + return -ENODEV; + + if (pci_resource_len(pdev, 0) < RISCV_IOMMU_REG_SIZE) + return -ENODEV; + + rc =3D pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); + if (rc) + return dev_err_probe(dev, rc, "pcim_iomap_regions failed\n"); + + iommu =3D devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); + if (!iommu) + return -ENOMEM; + + iommu->dev =3D dev; + iommu->reg =3D pcim_iomap_table(pdev)[0]; + + pci_set_master(pdev); + dev_set_drvdata(dev, iommu); + + /* Check device reported capabilities / features. */ + iommu->caps =3D riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAPABILITIES); + iommu->fctl =3D riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL); + + /* The PCI driver only uses MSIs, make sure the IOMMU supports this */ + switch (FIELD_GET(RISCV_IOMMU_CAPABILITIES_IGS, iommu->caps)) { + case RISCV_IOMMU_CAPABILITIES_IGS_MSI: + case RISCV_IOMMU_CAPABILITIES_IGS_BOTH: + break; + default: + return dev_err_probe(dev, -ENODEV, + "unable to use message-signaled interrupts\n"); + } + + /* Allocate and assign IRQ vectors for the various events */ + rc =3D pci_alloc_irq_vectors(pdev, 1, RISCV_IOMMU_INTR_COUNT, + PCI_IRQ_MSIX | PCI_IRQ_MSI); + if (rc <=3D 0) + return dev_err_probe(dev, -ENODEV, + "unable to allocate irq vectors\n"); + + iommu->irqs_count =3D rc; + for (vec =3D 0; vec < iommu->irqs_count; vec++) + iommu->irqs[vec] =3D msi_get_virq(dev, vec); + + /* Enable message-signaled interrupts, fctl.WSI */ + if (iommu->fctl & RISCV_IOMMU_FCTL_WSI) { + iommu->fctl ^=3D RISCV_IOMMU_FCTL_WSI; + riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl); + } + + return riscv_iommu_init(iommu); +} + +static void riscv_iommu_pci_remove(struct pci_dev *pdev) +{ + struct riscv_iommu_device *iommu =3D dev_get_drvdata(&pdev->dev); + + riscv_iommu_remove(iommu); +} + +static const struct pci_device_id riscv_iommu_pci_tbl[] =3D { + {PCI_VDEVICE(REDHAT, PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), 0}, + {PCI_VDEVICE(RIVOS, PCI_DEVICE_ID_RIVOS_RISCV_IOMMU_GA), 0}, + {0,} +}; + +static struct pci_driver riscv_iommu_pci_driver =3D { + .name =3D KBUILD_MODNAME, + .id_table =3D riscv_iommu_pci_tbl, + .probe =3D riscv_iommu_pci_probe, + .remove =3D riscv_iommu_pci_remove, + .driver =3D { + .suppress_bind_attrs =3D true, + }, +}; + +builtin_pci_driver(riscv_iommu_pci_driver); --=20 2.34.1