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Tue, 17 Mar 2026 12:16:07 -0700 From: Nicolin Chen To: , , , , CC: , , , , , , , , , , , Subject: [PATCH v2 5/7] iommu/arm-smmu-v3: Replace smmu with master in arm_smmu_inv Date: Tue, 17 Mar 2026 12:15:38 -0700 Message-ID: <5ea483632238b353cf491904cb0e81f51a9f8327.1773774441.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672E:EE_|SA1PR12MB9547:EE_ X-MS-Office365-Filtering-Correlation-Id: 762dd030-2f12-4f99-2d0a-08de8459b443 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700016|82310400026|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: t/BCP2Rn3NNpjqnu/G+Byort8X6Guwjn5kh82lgACodDfZsE3Y2ND1pc7WBY1HaxUwLFSu0QFCCAA+iw1LcuuRymz6kB8W3Uc0/A1S3vXpTV55cViKU1F0VjEjd40N17jomgyjOuM6aZrrKTM0rXv1Md0wyGFUQXQKwx4Fjp9EtSZzDFILYb0wLMHTIQtAjhfT4c/SOSEIqMhA9X54ooMx4PIK8qaalObnxpN1wRaGlwJxtrrhrXHz9SH494cbzXoNaBsMl5eS9U2D0GaBqn6u6GInV9yO140FH2YpO33NUHdTHzaE3rtu3sZAL2g5OulAX6eEexjgR4WN27+zZwtQao4hLjRHyKSanYdjlhtmUWm6NfVoMyAC8wKgFc6nHbJT+DbDKUVJ1wPosRptS044+YRN4VdevHMkbrB/QzmgxPVqMGWLZxeVQd898RnR1DCesXmxoIi6lz1rNM/53cCHWZ+76GbjAJ/eSh2Exiig8iBa659zyRN2/GZSmMGDhaC4zFdfI4EblLTjLEC34EOPO/h2mnkN8HF7JQL9pz+4t+VuTynWSSgJ9vJ1JDqhtvB0526teiRsxqE+znFtdfbNXS6yOI5+phqDjvbRyBJhJA4zIjgnnRmKAvUSbyyh8kZLcqN6WtrclxOHkvHCxi7usPDKIh43ORurCyf+2mv8RI98HpacvYC6sNRcsybT1bnt8sY8sxh3ePjv2Pxwt6JZob+cS1eFmiqcaVrogMh//H2z2ThaN8rFjP5noKnQ4PpI6W4tz8+IClGUj22ebvrQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700016)(82310400026)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; 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charset="utf-8" Storing master allows to backtrack the master pointer from an invalidation entry, which will be useful when handling ATC invalidation time outs. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 34 +++++++++++-------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 ++++++++------ 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 3eb12a34b086a..cb83ea1f3407f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -662,7 +662,7 @@ enum arm_smmu_inv_type { }; =20 struct arm_smmu_inv { - struct arm_smmu_device *smmu; + struct arm_smmu_master *master; u8 type; u8 size_opcode; u8 nsize_opcode; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index add671363c828..ef0c0bfe44206 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -653,39 +653,43 @@ static void arm_smmu_v3_invs_test_verify(struct kunit= *test, } } =20 +static struct arm_smmu_master invs_master =3D { + .smmu =3D &smmu, +}; + static struct arm_smmu_invs invs1 =3D { .num_invs =3D 3, - .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, - { .type =3D INV_TYPE_S2_VMID_S1_CLEAR, .id =3D 1, }, - { .type =3D INV_TYPE_ATS, .id =3D 3, }, }, + .inv =3D { { .master =3D &invs_master, .type =3D INV_TYPE_S2_VMID, .id = =3D 1, }, + { .master =3D &invs_master, .type =3D INV_TYPE_S2_VMID_S1_CLEAR, .id = =3D 1, }, + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 3, }, }, }; =20 static struct arm_smmu_invs invs2 =3D { .num_invs =3D 3, - .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ - { .type =3D INV_TYPE_ATS, .id =3D 4, }, - { .type =3D INV_TYPE_ATS, .id =3D 5, }, }, + .inv =3D { { .master =3D &invs_master, .type =3D INV_TYPE_S2_VMID, .id = =3D 1, }, /* dup */ + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 4, }, + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 5, }, }, }; =20 static struct arm_smmu_invs invs3 =3D { .num_invs =3D 3, - .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ - { .type =3D INV_TYPE_ATS, .id =3D 5, }, /* recover a trash */ - { .type =3D INV_TYPE_ATS, .id =3D 6, }, }, + .inv =3D { { .master =3D &invs_master, .type =3D INV_TYPE_S2_VMID, .id = =3D 1, }, /* dup */ + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 5, }, /* re= cover a trash */ + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 6, }, }, }; =20 static struct arm_smmu_invs invs4 =3D { .num_invs =3D 3, - .inv =3D { { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 1 }, - { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 3 }, - { .type =3D INV_TYPE_ATS, .id =3D 12, .ssid =3D 1 }, }, + .inv =3D { { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 10= , .ssid =3D 1 }, + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 10, .ssid = =3D 3 }, + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 12, .ssid = =3D 1 }, }, }; =20 static struct arm_smmu_invs invs5 =3D { .num_invs =3D 3, - .inv =3D { { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 2 }, - { .type =3D INV_TYPE_ATS, .id =3D 10, .ssid =3D 3 }, /* duplicate */ - { .type =3D INV_TYPE_ATS, .id =3D 12, .ssid =3D 2 }, }, + .inv =3D { { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 10= , .ssid =3D 2 }, + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 10, .ssid = =3D 3 }, /* dup */ + { .master =3D &invs_master, .type =3D INV_TYPE_ATS, .id =3D 12, .ssid = =3D 2 }, }, }; =20 static void arm_smmu_v3_invs_test(struct kunit *test) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9c8972ebc94f9..aa42fe39d66b6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1071,8 +1071,9 @@ arm_smmu_invs_iter_next(struct arm_smmu_invs *invs, s= ize_t next, size_t *idx) static int arm_smmu_inv_cmp(const struct arm_smmu_inv *inv_l, const struct arm_smmu_inv *inv_r) { - if (inv_l->smmu !=3D inv_r->smmu) - return cmp_int((uintptr_t)inv_l->smmu, (uintptr_t)inv_r->smmu); + if (inv_l->master->smmu !=3D inv_r->master->smmu) + return cmp_int((uintptr_t)inv_l->master->smmu, + (uintptr_t)inv_r->master->smmu); if (inv_l->type !=3D inv_r->type) return cmp_int(inv_l->type, inv_r->type); if (inv_l->id !=3D inv_r->id) @@ -2629,22 +2630,22 @@ static void arm_smmu_inv_to_cmdq_batch(struct arm_s= mmu_inv *inv, unsigned long iova, size_t size, unsigned int granule) { - if (arm_smmu_inv_size_too_big(inv->smmu, size, granule)) { + if (arm_smmu_inv_size_too_big(inv->master->smmu, size, granule)) { cmd->opcode =3D inv->nsize_opcode; - arm_smmu_cmdq_batch_add(inv->smmu, cmds, cmd); + arm_smmu_cmdq_batch_add(inv->master->smmu, cmds, cmd); return; } =20 cmd->opcode =3D inv->size_opcode; - arm_smmu_cmdq_batch_add_range(inv->smmu, cmds, cmd, iova, size, granule, - inv->pgsize); + arm_smmu_cmdq_batch_add_range(inv->master->smmu, cmds, cmd, iova, size, + granule, inv->pgsize); } =20 static inline bool arm_smmu_invs_end_batch(struct arm_smmu_inv *cur, struct arm_smmu_inv *next) { /* Changing smmu means changing command queue */ - if (cur->smmu !=3D next->smmu) + if (cur->master->smmu !=3D next->master->smmu) return true; /* The batch for S2 TLBI must be done before nested S1 ASIDs */ if (cur->type !=3D INV_TYPE_S2_VMID_S1_CLEAR && @@ -2671,7 +2672,7 @@ static void __arm_smmu_domain_inv_range(struct arm_sm= mu_invs *invs, if (READ_ONCE(cur->users)) break; while (cur !=3D end) { - struct arm_smmu_device *smmu =3D cur->smmu; + struct arm_smmu_device *smmu =3D cur->master->smmu; struct arm_smmu_cmdq_ent cmd =3D { /* * Pick size_opcode to run arm_smmu_get_cmdq(). This can @@ -2700,7 +2701,8 @@ static void __arm_smmu_domain_inv_range(struct arm_sm= mu_invs *invs, break; case INV_TYPE_S2_VMID_S1_CLEAR: /* CMDQ_OP_TLBI_S12_VMALL already flushed S1 entries */ - if (arm_smmu_inv_size_too_big(cur->smmu, size, granule)) + if (arm_smmu_inv_size_too_big(cur->master->smmu, size, + granule)) continue; cmd.tlbi.vmid =3D cur->id; arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); @@ -3225,7 +3227,7 @@ arm_smmu_master_build_inv(struct arm_smmu_master *mas= ter, { struct arm_smmu_invs *build_invs =3D master->build_invs; struct arm_smmu_inv *cur, inv =3D { - .smmu =3D master->smmu, + .master =3D master, .type =3D type, .id =3D id, .pgsize =3D pgsize, @@ -3261,6 +3263,7 @@ arm_smmu_master_build_inv(struct arm_smmu_master *mas= ter, case INV_TYPE_ATS: case INV_TYPE_ATS_FULL: cur->size_opcode =3D cur->nsize_opcode =3D CMDQ_OP_ATC_INV; + cur->master =3D master; cur->ssid =3D ssid; break; } @@ -3457,7 +3460,7 @@ static void arm_smmu_inv_flush_iotlb_tag(struct arm_s= mmu_inv *inv) } =20 cmd.opcode =3D inv->nsize_opcode; - arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); + arm_smmu_cmdq_issue_cmd_with_sync(inv->master->smmu, &cmd); } =20 /* Should be installed after arm_smmu_install_ste_for_dev() */ --=20 2.43.0