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Tue, 09 Sep 2025 19:09:23 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b61ba742f9sm17682681cf.10.2025.09.09.19.09.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 19:09:22 -0700 (PDT) From: Chen Wang To: kwilczynski@kernel.org, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de, bwawrzyn@cisco.com, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, 18255117159@163.com, inochiama@gmail.com, kishon@kernel.org, krzk+dt@kernel.org, lpieralisi@kernel.org, mani@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, s-vadapalli@ti.com, tglx@linutronix.de, thomas.richard@bootlin.com, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, rabenda.cn@gmail.com, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH v2 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042 Date: Wed, 10 Sep 2025 10:09:13 +0800 Message-Id: <5cecf3c854253e508a88995011dd4631fa0c6eae.1757467895.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. Signed-off-by: Inochi Amaoto Signed-off-by: Han Gao Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index b3e4d3c18fdc..b521f674283e 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 { #clock-cells =3D <1>; }; =20 + pcie_rc0: pcie@7060000000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + msi-parent =3D <&msi>; + status =3D "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + msi-parent =3D <&msi>; + status =3D "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + msi-parent =3D <&msi>; + status =3D "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + linux,pci-domain =3D <3>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000= >, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + msi-parent =3D <&msi>; + status =3D "disabled"; + }; + clint_mswi: interrupt-controller@7094000000 { compatible =3D "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg =3D <0x00000070 0x94000000 0x00000000 0x00004000>; --=20 2.34.1