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Mon, 24 Jul 2023 17:08:19 +0800 (CST) MIME-Version: 1.0 Date: Mon, 24 Jul 2023 17:08:19 +0800 From: sunran001@208suo.com To: alexander.deucher@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line In-Reply-To: <20230724090624.9699-1-xujianghui@cdjrlc.com> References: <20230724090624.9699-1-xujianghui@cdjrlc.com> User-Agent: Roundcube Webmail Message-ID: <5ce64e06635dbf038d73452098fd0163@208suo.com> X-Sender: sunran001@208suo.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8"; format="flowed" ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun --- .../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h | 21 +++++++------------ 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h=20 b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h index eadbe0149cae..eb694f9f556d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h @@ -41,8 +41,7 @@ #define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8=20 Table Version 0.2 #define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving=20 Clock Table Version 1.00 -enum SMU_13_0_7_ODFEATURE_CAP -{ +enum SMU_13_0_7_ODFEATURE_CAP { SMU_13_0_7_ODCAP_GFXCLK_LIMITS =3D 0, SMU_13_0_7_ODCAP_UCLK_LIMITS, SMU_13_0_7_ODCAP_POWER_LIMIT, @@ -62,8 +61,7 @@ enum SMU_13_0_7_ODFEATURE_CAP SMU_13_0_7_ODCAP_COUNT, }; -enum SMU_13_0_7_ODFEATURE_ID -{ +enum SMU_13_0_7_ODFEATURE_ID { SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS =3D 1 <<=20 SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature SMU_13_0_7_ODFEATURE_UCLK_LIMITS =3D 1 <<=20 SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature SMU_13_0_7_ODFEATURE_POWER_LIMIT =3D 1 <<=20 SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature @@ -85,8 +83,7 @@ enum SMU_13_0_7_ODFEATURE_ID #define SMU_13_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features -enum SMU_13_0_7_ODSETTING_ID -{ +enum SMU_13_0_7_ODSETTING_ID { SMU_13_0_7_ODSETTING_GFXCLKFMAX =3D 0, SMU_13_0_7_ODSETTING_GFXCLKFMIN, SMU_13_0_7_ODSETTING_UCLKFMIN, @@ -123,8 +120,7 @@ enum SMU_13_0_7_ODSETTING_ID }; #define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings -enum SMU_13_0_7_PWRMODE_SETTING -{ +enum SMU_13_0_7_PWRMODE_SETTING { SMU_13_0_7_PMSETTING_POWER_LIMIT_QUIET =3D 0, SMU_13_0_7_PMSETTING_POWER_LIMIT_BALANCE, SMU_13_0_7_PMSETTING_POWER_LIMIT_TURBO, @@ -144,8 +140,7 @@ enum SMU_13_0_7_PWRMODE_SETTING }; #define SMU_13_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode=20 Settings -struct smu_13_0_7_overdrive_table -{ +struct smu_13_0_7_overdrive_table { uint8_t revision; //Revision =3D=20 SMU_13_0_7_PP_OVERDRIVE_VERSION uint8_t reserve[3]; //Zero filled field=20 reserved for future use uint32_t feature_count; //Total number of=20 supported features @@ -156,8 +151,7 @@ struct smu_13_0_7_overdrive_table int16_t pm_setting[SMU_13_0_7_MAX_PMSETTING]; //Optimized power=20 mode feature settings }; -enum SMU_13_0_7_PPCLOCK_ID -{ +enum SMU_13_0_7_PPCLOCK_ID { SMU_13_0_7_PPCLOCK_GFXCLK =3D 0, SMU_13_0_7_PPCLOCK_SOCCLK, SMU_13_0_7_PPCLOCK_UCLK, @@ -175,8 +169,7 @@ enum SMU_13_0_7_PPCLOCK_ID }; #define SMU_13_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks -struct smu_13_0_7_powerplay_table -{ +struct smu_13_0_7_powerplay_table { struct atom_common_table_header header; //For PLUM_BONITO,=20 header.format_revision =3D 15, header.content_revision =3D 0 uint8_t table_revision; //For PLUM_BONITO,=20 table_revision =3D 2 uint8_t padding;