From nobody Sun Jun 28 08:39:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79C7CC433F5 for ; Wed, 9 Feb 2022 21:04:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232816AbiBIVEj (ORCPT ); Wed, 9 Feb 2022 16:04:39 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:54956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232762AbiBIVEe (ORCPT ); Wed, 9 Feb 2022 16:04:34 -0500 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EA92C033255 for ; Wed, 9 Feb 2022 13:04:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644440677; x=1675976677; h=date:from:to:cc:subject:message-id:mime-version; bh=9WFgncTQailPw0fCuxpKTUIeFrcwnCEtfpmUPBiT+Zg=; b=dpLoguLEY9t2TFtVeHbzyThtW2oSsiYEQbzS4XZaq/7QNJhAur4dn+2+ cj/hs8haeyfGETEl1l+CMgZYlfPkiIrwDKPF9muJISmFYKXsUx3N0Xr+m rzid2pycZil+1sq/nO6+AdI4lH5qUfia1iNSx7KQRMDEQdPTgHToDBENP 6NCCCiaqvVmX0DvyyahjSuE8ScB/lo7kSsUho8TufyoCgYv3hyQ+4cbZi R1hb7cah84krsnMZhEYgvelTsq9SoOlL0fKbOrLaHTdEI8Gvrq+DFBZ2F 7wvW4Hzeot7JpGN+ZY5xK6KBL0W8DwqRSJQ5hmGKS+smJ2kQgNp4TDcIG g==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="246914846" X-IronPort-AV: E=Sophos;i="5.88,356,1635231600"; d="scan'208";a="246914846" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 13:04:36 -0800 X-IronPort-AV: E=Sophos;i="5.88,356,1635231600"; d="scan'208";a="701411368" Received: from guptapa-mobl1.amr.corp.intel.com ([10.251.3.164]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 13:04:36 -0800 Date: Wed, 9 Feb 2022 13:04:36 -0800 From: Pawan Gupta To: Thomas Gleixner , Borislav Petkov Cc: Ingo Molnar , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andi Kleen , Tony Luck , linux-kernel@vger.kernel.org, antonio.gomez.iglesias@linux.intel.com, neelima.krishnan@intel.com Subject: [PATCH] x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits Message-ID: <5bd785a1d6ea0b572250add0c6617b4504bc24d1.1644440311.git.pawan.kumar.gupta@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" tsx_clear_cpuid() uses MSR_TSX_FORCE_ABORT to clear CPUID.RTM and CPUID.HLE. Not all CPUs support MSR_TSX_FORCE_ABORT, alternatively use MSR_IA32_TSX_CTRL when supported. Fixes: 293649307ef9 ("x86/tsx: Clear CPUID bits when TSX always force abort= s") Reported-by: kernel test robot Tested-by: Neelima Krishnan Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/tsx.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c index 9c7a5f049292..c2343ea911e8 100644 --- a/arch/x86/kernel/cpu/tsx.c +++ b/arch/x86/kernel/cpu/tsx.c @@ -58,7 +58,7 @@ void tsx_enable(void) wrmsrl(MSR_IA32_TSX_CTRL, tsx); } =20 -static bool __init tsx_ctrl_is_supported(void) +static bool tsx_ctrl_is_supported(void) { u64 ia32_cap =3D x86_read_arch_cap_msr(); =20 @@ -97,6 +97,10 @@ void tsx_clear_cpuid(void) rdmsrl(MSR_TSX_FORCE_ABORT, msr); msr |=3D MSR_TFA_TSX_CPUID_CLEAR; wrmsrl(MSR_TSX_FORCE_ABORT, msr); + } else if (tsx_ctrl_is_supported()) { + rdmsrl(MSR_IA32_TSX_CTRL, msr); + msr |=3D TSX_CTRL_CPUID_CLEAR; + wrmsrl(MSR_IA32_TSX_CTRL, msr); } } =20 @@ -106,13 +110,11 @@ void __init tsx_init(void) int ret; =20 /* - * Hardware will always abort a TSX transaction if both CPUID bits - * RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are set. In this case, it is - * better not to enumerate CPUID.RTM and CPUID.HLE bits. Clear them - * here. + * Hardware will always abort a TSX transaction when CPUID + * RTM_ALWAYS_ABORT is set. In this case, it is better not to enumerate + * CPUID.RTM and CPUID.HLE bits. Clear them here. */ - if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) && - boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { + if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { tsx_ctrl_state =3D TSX_CTRL_RTM_ALWAYS_ABORT; tsx_clear_cpuid(); setup_clear_cpu_cap(X86_FEATURE_RTM); --=20 2.31.1