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[95.235.217.160]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c822fsm189865966b.138.2024.05.10.07.35.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 07:35:28 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Eric Anholt , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v2 4/4] arm64: dts: broadcom: Add support for BCM2712 Date: Fri, 10 May 2024 16:35:30 +0200 Message-ID: <59a3015c3a6f2f0b70a38c030274a163773e7757.1715332922.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta --- arch/arm64/boot/dts/broadcom/Makefile | 1 + .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 62 ++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 302 ++++++++++++++++++ 3 files changed, 365 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/br= oadcom/Makefile index 8b4591ddd27c..92565e9781ad 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -6,6 +6,7 @@ DTC_FLAGS :=3D -@ dtb-$(CONFIG_ARCH_BCM2835) +=3D bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ + bcm2712-rpi-5-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/= boot/dts/broadcom/bcm2712-rpi-5-b.dts new file mode 100644 index 000000000000..b5921437e09f --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "bcm2712.dtsi" + +/ { + compatible =3D "raspberrypi,5-model-b", "brcm,bcm2712"; + model =3D "Raspberry Pi 5"; + + aliases { + serial10 =3D &uart0; + }; + + chosen: chosen { + stdout-path =3D "serial10:115200n8"; + }; + + /* Will be filled by the bootloader */ + memory@0 { + device_type =3D "memory"; + reg =3D <0 0 0x28000000>; + }; + + sd_io_1v8_reg: sd-io-1v8-reg { + compatible =3D "regulator-gpio"; + regulator-name =3D "vdd-sd-io"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us =3D <5000>; + gpios =3D <&gio_aon 3 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1>, + <3300000 0x0>; + }; + + sd_vcc_reg: sd-vcc-reg { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&gio_aon 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* The system UART */ +&uart0 { + status =3D "okay"; +}; + +/* SDIO1 is used to drive the SD card */ +&sdio1 { + vqmmc-supply =3D <&sd_io_1v8_reg>; + vmmc-supply =3D <&sd_vcc_reg>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dt= s/broadcom/bcm2712.dtsi new file mode 100644 index 000000000000..398df13148bd --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/ { + compatible =3D "brcm,bcm2712"; + + #address-cells =3D <2>; + #size-cells =3D <1>; + + interrupt-parent =3D <&gicv2>; + + axi: axi { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + sdio1: mmc@1000fff000 { + compatible =3D "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg =3D <0x10 0x00fff000 0x260>, + <0x10 0x00fff400 0x200>; + reg-names =3D "host", "cfg"; + interrupts =3D ; + clocks =3D <&clk_emmc2>; + clock-names =3D "sw_sdio"; + mmc-ddr-3_3v; + }; + + gicv2: interrupt-controller@107fff9000 { + interrupt-controller; + #interrupt-cells =3D <3>; + compatible =3D "arm,gic-400"; + reg =3D <0x10 0x7fff9000 0x1000>, + <0x10 0x7fffa000 0x2000>, + <0x10 0x7fffc000 0x2000>, + <0x10 0x7fffe000 0x2000>; + interrupts =3D ; + }; + }; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "osc"; + clock-frequency =3D <54000000>; + }; + + clk_vpu: clk-vpu { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <750000000>; + clock-output-names =3D "vpu-clock"; + }; + + clk_uart: clk-uart { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <9216000>; + clock-output-names =3D "uart-clock"; + }; + + clk_emmc2: clk-emmc2 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + clock-output-names =3D "emmc2-clock"; + }; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* Source for d/i cache-line-size, cache-sets, cache-size + * https://developer.arm.com/documentation/100798/0401 + * /L1-memory-system/About-the-L1-memory-system?lang=3Den + */ + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x000>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l0>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x100>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l1>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x200>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x300>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l3>; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100798/0401 + * /L2-memory-system/About-the-L2-memory-system?lang=3Den + * and for cache-size: + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2712 + */ + l2_cache_l0: l2-cache-l0 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=3Den + * Source for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#b= cm2712 + */ + l3_cache: l3-cache { + compatible =3D "cache"; + cache-size =3D <0x200000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; // 2MiB(size)/64(line-size)=3D32768ways/16-way s= et + cache-level =3D <3>; + cache-unified; + }; + }; + + psci { + method =3D "smc"; + compatible =3D "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + cpu_on =3D <0xc4000003>; + cpu_suspend =3D <0xc4000001>; + cpu_off =3D <0x84000002>; + }; + + rmem: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + atf@0 { + reg =3D <0x0 0x0 0x80000>; + no-map; + }; + + cma: linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + alloc-ranges =3D <0x0 0x00000000 0x40000000>; + }; + }; + + soc: soc@107c000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x7c000000 0x10 0x7c000000 0x04000000>; + /* Emulate a contiguous 30-bit address range for DMA */ + dma-ranges =3D <0xc0000000 0x00 0x00000000 0x40000000>, + <0x7c000000 0x10 0x7c000000 0x04000000>; + + system_timer: timer@7c003000 { + compatible =3D "brcm,bcm2835-system-timer"; + reg =3D <0x7c003000 0x1000>; + interrupts =3D , + , + , + ; + clock-frequency =3D <1000000>; + }; + + mailbox: mailbox@7c013880 { + compatible =3D "brcm,bcm2835-mbox"; + reg =3D <0x7c013880 0x40>; + interrupts =3D ; + #mbox-cells =3D <0>; + }; + + local_intc: local-intc@7cd00000 { + compatible =3D "brcm,bcm2836-l1-intc"; + reg =3D <0x7cd00000 0x100>; + }; + + uart0: serial@7d001000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x7d001000 0x200>; + interrupts =3D ; + clocks =3D <&clk_uart>, <&clk_vpu>; + clock-names =3D "uartclk", "apb_pclk"; + arm,primecell-periphid =3D <0x00241011>; + status =3D "disabled"; + }; + + interrupt-controller@7d517000 { + compatible =3D "brcm,bcm7271-l2-intc"; + reg =3D <0x7d517000 0x10>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + status =3D "disabled"; + }; + + gio_aon: gpio@7d517c00 { + compatible =3D "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg =3D <0x7d517c00 0x40>; + gpio-controller; + #gpio-cells =3D <2>; + // Don't use GIO_AON as an interrupt controller because it will + // clash with the firmware monitoring the PMIC interrupt via the VPU. + brcm,gpio-bank-widths =3D <17 6>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + /* This only applies to the ARMv7 stub */ + arm,cpu-registers-not-fw-configured; + }; +}; --=20 2.35.3